11.1 Layout Guidelines

The LP8731-Q1 is a monolithic device with integrated power FETs. For that reason, it is important to pay special attention to the use of appropriate to input, output, power, and ground track dimensions in the PCB layout in order to achieve low impedance small current loop paths and tracks with adequate current density to carry the target currents.

The device pin solder bumps are arranged with power and ground bumps at the edges of the package to facilitate PCB layout considerations. This enables using the top metal layer to route the power and ground tracks. Thus, the current loops for the bucks can be very short and this also makes placing the bypass caps on the device side of the PCB possible. (See Figure 31.) Avoid using vias to tap power and ground planes for the switcher supply pins, because they can be very inductive and could incur large i*dv/dt transient voltage drops. If vias are unavoidable, use them liberally to minimize the impedance they may present.

For more information on board layout techniques, refer to Texas Instruments AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009). This application note also discusses recommended PCB pad geometry, package handling, solder stencil and the assembly process. See also Texas Instruments AN-1229 SIMPLE SWITCHER^® PCB Layout Guidelines (SNVA054) and Texas Instruments AN-2078 PCB Layout for Texas Instrument' SIMPLE SWITCHER® Power Modules (SNVA452).

11.2 Layout Example

Figure 31. LP8731-Q1 Layout Example