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SNVSA28 December 2014 LP8731-Q1

PRODUCTION DATA.

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YZR|25
- MXBG279

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snvsa28_oa

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
V_IN, SDA, SCL	−0.3	6	V
GND to GND SLUG		±0.3	V
Power dissipation (P_{D_MAX})	Internally limited
Junction temperature (T_J-MAX)		150	°C
Maximum lead temperature (soldering)		260
Storage temperature (T_stg )	–65	150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions (Bucks)

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
V_IN	2.8	5.5	V
V_EN	0	(V_IN + 0.3)	V
Junction temperature (T_J)	–40	125	°C
Ambient temperature (T_A)	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LP8731-Q1	UNIT
		DSBGA (YZR)
		25 PINS
R_θJA	Junction-to-ambient thermal resistance	58.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.3
R_θJB	Junction-to-board thermal resistance	8
ψ_JT	Junction-to-top characterization parameter	0.6
ψ_JB	Junction-to-board characterization parameter	8
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 General Electrical Characteristics

Unless otherwise noted, V_IN = 3.6 V. Typical values and limits apply for T_J = 25°C.⁽¹⁾

PARAMETER		TEST CONDITIONS	TYP	UNIT
I_Q	VINLDO12 shutdown current	V_IN = 3.6 V	3	µA
V_POR	Power-on reset threshold	V_DD Falling Edge⁽²⁾	1.9	V
T_SD	Thermal shutdown threshold		160	°C
T_SDH	Thermal shutdown hysteresis		20	°C
UVLO	Undervoltage lockout	Rising	2.9	V
UVLO	Undervoltage lockout	Falling	2.7	V

(1) All voltages are with respect to the potential at the GND pin.

(2) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.

7.6 Low Dropout Regulators, LDO1 And LDO2

Unless otherwise noted, V_IN = 3.6 V, C_IN = 1 µF, C_OUT = 0.47 µF. Typical values and limits apply for T_J = 25°C.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IN	Operational voltage range	VINLDO1 and VINLDO2 PMOS pins⁽⁴⁾	2.45⁽⁵⁾		5.5⁽⁵⁾	V
V_OUT Accuracy	Output voltage accuracy (default V_OUT)	Load current = 1 mA	−3%⁽⁵⁾		3%⁽⁵⁾
ΔV_OUT	Line regulation	V_IN = (V_OUT + 0.3 V) to 5 V⁽⁶⁾ Load current = 1 mA			0.2⁽⁵⁾	%/V
ΔV_OUT	Load regulation	V_IN = 3.6 V, Load current = 1 mA to I_MAX			0.011⁽⁵⁾	%/mA
I_SC	Short circuit current limit	LDO1 to LDO2, V_OUT = 0 V		500		mA
V_IN – V_OUT	Dropout voltage	Load current = 50 mA at V_OUT = 2.8 V⁽⁷⁾		30	50⁽⁵⁾	mV
V_IN – V_OUT	Dropout voltage	Load current = 250 mA at V_OUT = 2.8 V		150	200⁽⁵⁾	mV
PSRR	Power supply ripple rejection	ƒ = 10 kHz, Load current = I_MAX		45		dB
θn	Supply output noise	10 Hz < F < 100 KHz		280		µVrms
I_Q⁽⁸⁾⁽⁹⁾	Quiescent current “on”	I_OUT = 0 mA		40		µA
	Quiescent current “on”	I_OUT = I_MAX		60		µA
	Quiescent current “off”	EN is de-asserted⁽¹⁰⁾		0.03		µA
T_ON	Turn-on time	Start-up from shutdown		300		µs
C_OUT	Output capacitance	Capacitance for stability 0°C ≤ T_J ≤ 125°C	0.33	0.47		µF
		−40°C ≤ T_J ≤ 125°C	0.68	1		µF
		ESR	5		500	mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) Pins A1 and/or A5 can operate from V_IN min of 1.74 to a V_IN max of 5.5 V. This rating is only for the series pass PMOS power FET. It allows the system design to use a lower voltage rating if the input voltage comes from a buck output. However, if V_IN is required to operate at a higher voltage than other device supply pins, it is necessary to wire the VINLDO12 pins (B4 an B5) and VINLDO1 and VINLDO2 pins (A1 and/or A5) together to that higher voltage so that the LDO core supply has sufficient head-room to operate the gate of the PMOS.

(5) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C.

(6) V_IN minimum for line regulation values is 1.8 V.

(7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its nominal value.

(8) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT.

(9) The I_Q can be defined as the standing current of the LP8731-Q1 when the I²C bus is activated and all other power blocks have been disabled via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP8731-Q1 is powered using a battery.

(10) The I_Q exhibits a higher current draw when the EN pin is de-asserted because the I²C buffer pins draw an additional 2 µA.

7.7 Buck Converters SW1, SW2

Unless otherwise noted, V_IN = 3.6 V, C_IN = 10 µF, C_OUT = 10 µF, L_OUT = 2.2 µH ceramic. Typical values and limits apply for T_J = 25°C.⁽¹⁾⁽²⁾⁽³⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_FB	Feedback voltage		−3%⁽⁴⁾		3%⁽⁴⁾
V_OUT	Line regulation	2.8 V < V_IN < 5.5 V I_OUT = 10 mA		0.089%		/V
	Load regulation	100 mA < I_O < I_MAX		0.0013%		/mA
	Output accuracy⁽⁵⁾	V_IN = 3.3 V, V_OUT from 0.8875 V to 1.1625 V Load from 0 mA to 600 mA	–2%⁽⁴⁾		2%⁽⁴⁾
Eff	Efficiency	Load current = 250 mA		90%
I_SHDN	Shutdown supply current	EN is de-asserted		0.01		µA
f_OSC	Internal oscillator frequency		1.7⁽⁴⁾	2.1		MHz
I_PEAK	Buck1 peak switching current limit			1.7		A
I_PEAK	Buck2 peak switching current limit			1.7		A
I_Q⁽⁶⁾	Quiescent current “on”	No load PWM Mode		2		mA
R_DSON (P)	Pin-pin resistance PFET			200		mΩ
R_DSON (N)	Pin-pin resistance NFET			180		mΩ
T_ON	Turn-on time	Start-up from shutdown		500		µs
C_IN	Input capacitance	Capacitance for stability	10			µF
C_O	Output capacitance	Capacitance for stability	10			µF

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C

(5) Based on closed loop, bench test data with LP8731YZREVM.

(6) The I_Q can be defined as the standing current of the LP8731-Q1 when the I²C bus is active and all other power blocks have been disabled via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition. These two values can be used by the system designer when the LP8731-Q1 is powered using a battery.

7.8 I/O Electrical Characteristics

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IL	Input low level				0.4⁽¹⁾	V
V_IH	Input high level		1.2⁽¹⁾			V

(1) This specification is ensured by design.

7.9 Power-On Reset Threshold/Function (POR)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
nPOR	nPOR = Power-on reset for Buck1 and Buck2	Default	50		µs
nPOR threshold	Percentage of target voltage Buck1 or Buck2	V_BUCK1 AND V_BUCK2 rising	94%
nPOR threshold	Percentage of target voltage Buck1 or Buck2	V_BUCK1 OR V_BUCK2 falling	85%
V_OL	Output level low	Load = I_OL = 0.2 mA	0.23	0.5⁽¹⁾	V

(1) This specification is ensured by design.

7.10 I²C-Compatible Interface Timing

Unless otherwise noted, V_IN = 3.6 V. Nominal values and limits apply for T_J = 25°C.⁽¹⁾

			MIN	NOM	MAX	UNIT
ƒ_CLK	Clock frequency				400	kHz
t_BF	Bus-free time between start and stop	See⁽¹⁾	1.3			µs
t_HOLD	Hold time repeated start condition	See⁽¹⁾	0.6			µs
t_CLKLP	CLK low period	See⁽¹⁾	1.3			µs
t_CLKHP	CLK high period	See⁽¹⁾	0.6			µs
t_SU	Setup time repeated start condition	See⁽¹⁾	0.6			µs
t_DATAHLD	Data hold time	See⁽¹⁾	0			µs
t_DATASU	Data setup time	See⁽¹⁾	100			ns
T_SU	Setup time for start condition	See⁽¹⁾	0.6			µs
T_TRANS	Maximum pulse width of spikes that must be suppressed by the input filter of both DATA & CLK signals	See⁽¹⁾		50		ns

(1) This specification is ensured by design.

7.11 Typical Characteristics

T_A = 25°C unless otherwise noted

V_IN = 3.6 V	V_OUT = 2.6 V	100-mA load

Figure 1. Output Voltage Change vs. Temperature (LDO1)

V_OUT = 3.6 V	I_LOAD = 0 to 300 mA
V_OUT = 1.8 V	Tr = Tf = 1 µs

Figure 3. Load Transient 1-µs Edge Rate

V_IN = 3.6 V to 4.2 V	I_LOAD = 300 mA
V_OUT = 1.8 V	Tr = Tf = 20 µs

Figure 5. Line Transient 300-mA, 4-µs Edge Rate

I_OUT = 200 mA to 1.2 A PWM

Figure 7. Buck Load Transient PWM Mode

V_IN Step	I_OUT = 1.2 A	Tr = Tf = 10 µs

Figure 9. Buck Line Transient PWM

V_IN = 3.6 V	V_OUT = 3.3 V	100-mA load

Figure 2. Output Voltage Change vs. Temperature (LDO2)

V_OUT = 3.6 V	I_LOAD = 0 to 300 mA
V_OUT = 1.8 V	Tr = Tf = 4 µs

Figure 4. Load Transient 4-µs Edge Rate

V_IN = 3.6 V to 4.2 V	I_OUT = 1 mA
V_OUT = 1.8 V	Tr = Tf = 30 µs

Figure 6. Line Transient 1-mA, 30-µs Edge Rate

V_IN Step	I_OUT = 300 mA	Tr = Tf = 30 µs

Figure 8. Buck Line Transient PWM

V_IN Step	I_OUT = 1.2 A	Tr = Tf = 30 µs

Figure 10. Buck Line Transient PWM

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7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions (Bucks)

7.4 Thermal Information

7.5 General Electrical Characteristics

7.6 Low Dropout Regulators, LDO1 And LDO2

7.7 Buck Converters SW1, SW2

7.8 I/O Electrical Characteristics

7.9 Power-On Reset Threshold/Function (POR)

7.10 I2C-Compatible Interface Timing

7.11 Typical Characteristics

7.10 I²C-Compatible Interface Timing