米6体育平台手机版

ZHCSH29B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RNF|26

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.3.2 Sync Clock Functionality

The LP87524B/J/P-Q1 device contains a CLKIN input to synchronize switching clock of the buck regulator with the external clock. The block diagram of the clocking and PLL module is shown in Figure 7. Depending on the PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in PLL_CTRL register) and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside accuracy limits (–30%/+10%) for valid clock detection.

The NO_SYNC_CLK interrupt (in INT_TOP1 register) is also generated in cases the external clock is expected but it is not available. These cases are start-up (read OTP-to-STANDBY transition) when PLL_MODE[1:0] = 01 and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10.

LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 Clock_PLL.gif

Figure 7. Clock and PLL Module

Table 2. PLL Operation

DEVICE OPERATION MODE	PLL_MODE[1:0]	PLL AND CLOCK DETECTOR STATE	INTERRUPT FOR EXTERNAL CLOCK	CLOCK
STANDBY	00	Disabled	No	Internal RC
ACTIVE	00	Disabled	No	Internal RC
STANDBY	01	Enabled	When external clock appears or disappears	Automatic change to external clock when available
ACTIVE	01	Enabled	When external clock appears or disappears	Automatic change to external clock when available
STANDBY	10	Disabled	No	Internal RC
ACTIVE	10	Enabled	When external clock appears or disappears	Automatic change to external clock when available
STANDBY	11	Reserved
ACTIVE	11	Reserved