ZHCSH29B April   2017  – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
    1.     简化原理图
  3. 3 说明
    1.     效率与输出电流间的关系
  4. 4 修订历史记录
    1.     Device Images
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 DC-DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  OTP_REV
        2. 7.6.1.2  BUCK0_CTRL1
        3. 7.6.1.3  BUCK1_CTRL1
        4. 7.6.1.4  BUCK2_CTRL1
        5. 7.6.1.5  BUCK3_CTRL1
        6. 7.6.1.6  BUCK0_VOUT
        7. 7.6.1.7  BUCK0_FLOOR_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  BUCK1_FLOOR_VOUT
        10. 7.6.1.10 BUCK2_VOUT
        11. 7.6.1.11 BUCK2_FLOOR_VOUT
        12. 7.6.1.12 BUCK3_VOUT
        13. 7.6.1.13 BUCK3_FLOOR_VOUT
        14. 7.6.1.14 BUCK0_DELAY
        15. 7.6.1.15 BUCK1_DELAY
        16. 7.6.1.16 BUCK2_DELAY
        17. 7.6.1.17 BUCK3_DELAY
        18. 7.6.1.18 GPIO2_DELAY
        19. 7.6.1.19 GPIO3_DELAY
        20. 7.6.1.20 RESET
        21. 7.6.1.21 CONFIG
        22. 7.6.1.22 INT_TOP1
        23. 7.6.1.23 INT_TOP2
        24. 7.6.1.24 INT_BUCK_0_1
        25. 7.6.1.25 INT_BUCK_2_3
        26. 7.6.1.26 TOP_STAT
        27. 7.6.1.27 BUCK_0_1_STAT
        28. 7.6.1.28 BUCK_2_3_STAT
        29. 7.6.1.29 TOP_MASK1
        30. 7.6.1.30 TOP_MASK2
        31. 7.6.1.31 BUCK_0_1_MASK
        32. 7.6.1.32 BUCK_2_3_MASK
        33. 7.6.1.33 SEL_I_LOAD
        34. 7.6.1.34 I_LOAD_2
        35. 7.6.1.35 I_LOAD_1
        36. 7.6.1.36 PGOOD_CTRL1
        37. 7.6.1.37 PGOOD_CTRL2
        38. 7.6.1.38 PGOOD_FLT
        39. 7.6.1.39 PLL_CTRL
        40. 7.6.1.40 PIN_FUNCTION
        41. 7.6.1.41 GPIO_CONFIG
        42. 7.6.1.42 GPIO_IN
        43. 7.6.1.43 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RNF|26
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.1.1 Overview

The LP87524B/J/P-Q1 includes four step-down DC-DC converter cores configured for four single-phase outputs. The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to optimize the regulator operation for each application.

The LP87524B/J/P-Q1 has the following features:

  • DVS support
  • Automatic mode control based on the loading (PFM or PWM mode)
  • Forced-PWM mode operation
  • Optional external clock input to minimize crosstalk
  • Optional spread spectrum technique to reduce EMI
  • Phase control for optimized EMI
  • Synchronous rectification
  • Current mode loop with PI compensator
  • Soft start
  • Power Good flag with maskable interrupt
  • Power Good signal (PGOOD) with selectable sources
  • Average output current sensing (for PFM entry and load current measurement)

The following parameters can be programmed via registers:

  • Output voltage
  • Forced-PWM operation
  • Enable and disable delays for regulators and GPIOs controlled by ENx pins

There are two modes of operation for the converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced-PWM mode is disabled.

A multi-phase synchronous buck converter offers several advantages over a single power stage converter. For application processor power delivery, lower ripple on the input and output currents and faster transient response to load steps are the most significant advantages. Also, because the load current is evenly shared among multiple channels in multi-phase output configuration, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional to square of current. The physical size of the output inductor shrinks significantly due to this heat reduction. A block diagram of a single core is shown in Figure 5.

LP87524B-Q1 LP87524J-Q1 LP87524P-Q1 30190604.gifFigure 5. Detailed Block Diagram Showing One Core
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