Table 6. Design Parameters

8.2.2.1 Inductor Selection

The DC bias current characteristics of inductors must be considered. Different manufacturers follow different saturation current rating specifications, so attention must be given to details. (Please request DC bias curves from the manufacturer as part of the inductor selection process.) Minimum effective value of inductance to ensure good performance is 0.25 µH at 2.5 A (Default I_LIMITP typical) bias current over the inductor's operating temperature range. The inductor’s DC resistance should be less than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle load. Table 7 lists suggested inductors and suppliers. Shielded inductors radiate less noise and are preferable.

8.2.2.2 Input Capacitor Selection

A ceramic input capacitor of 10 µF, 10 V is sufficient for most applications. Place the input capacitor as close as possible to the VINBXX pin and GND pin of the device. A larger value or higher voltage rating may be used to improve input voltage filtering. Use X7R or X5R types, do not use Y5V. DC bias characteristics of ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input capacitance to ensure good performance is 2.5 µF at maximum input voltage DC bias including tolerances and over ambient temp range, assuming that there is at least 22 µF of additional capacitance common for all the power input pins on the system power rail.

The input filter capacitor supplies current to the PFET (high-side) switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance (ESR) provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating.

For additional noise immunity, adding a high-frequency decoupling capacitor of 100 nF to 1 µF between VDDA5V pin and GND is recommended.

8.2.2.3 Output Capacitor Selection

Use ceramic capacitor, X7R or X5R types; do not use Y5V. DC bias voltage characteristics of ceramic capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias curves should be requested from them as part of the capacitor selection process. The output filter capacitor smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR to perform these functions. Minimum effective output capacitance to ensure good performance in 6-phase configuration is 30 µF at the output voltage DC bias including tolerances and over ambient temp range.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its R_ESR. The R_ESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the switching frequency of the part.

A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as decreasing the PFM switching frequency. For most 6-phase applications 4 x 22-µF 0603 capacitors for C_OUT is suitable. Although the converter's loop compensation can be programmed to adapt to virtually several hundreds of microfarads C_OUT, an effective C_OUT less than 120 µF is preferred -- there is not necessarily any benefit to having a C_OUT higher than 120 µF. Note that the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required to settle V_OUT down as a consequence of the increased time constant.

8.2.2.4 LDO Capacitor Selection

A ceramic low ESR 1-μF capacitor should be connected between the VLDO and GNDA pins.

8.2.2.5 VIOSYS Capacitor Selection

Adding a ceramic low ESR 1-μF capacitor between the VIOSYS pin and GND is recommended. If V_VIOSYS signal is low noisy the capacitor is not required.