ZHCSJ52A December 2019 – August 2021 LP875701-Q1
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Descriptions
- 7.3.1 Multi-Phase DC/DC Converters
- 7.3.2 Sync Clock Functionality
- 7.3.3 Power-Up
- 7.3.4 Regulator Control
- 7.3.5 Enable and Disable Sequences
- 7.3.6 Device Reset Scenarios
- 7.3.7 Diagnosis and Protection Features
- 7.3.8 GPIO Signal Operation
- 7.3.9 Digital Signal Filtering
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1
Register Descriptions
- 53
- 7.6.1.1 DEV_REV
- 7.6.1.2 OTP_REV
- 7.6.1.3 BUCK0_CTRL1
- 7.6.1.4 BUCK0_DELAY
- 7.6.1.5 GPIO2_DELAY
- 7.6.1.6 GPIO3_DELAY
- 7.6.1.7 RESET
- 7.6.1.8 CONFIG
- 7.6.1.9 INT_TOP1
- 7.6.1.10 INT_TOP2
- 7.6.1.11 INT_BUCK_0_1
- 7.6.1.12 INT_BUCK_2_3
- 7.6.1.13 TOP_STAT
- 7.6.1.14 BUCK_0_1_STAT
- 7.6.1.15 BUCK_2_3_STAT
- 7.6.1.16 TOP_MASK1
- 7.6.1.17 TOP_MASK2
- 7.6.1.18 BUCK_0_1_MASK
- 7.6.1.19 BUCK_2_3_MASK
- 7.6.1.20 SEL_I_LOAD
- 7.6.1.21 I_LOAD_2
- 7.6.1.22 I_LOAD_1
- 7.6.1.23 PGOOD_CTRL1
- 7.6.1.24 PGOOD_CTRL2
- 7.6.1.25 PGOOD_FLT
- 7.6.1.26 PLL_CTRL
- 7.6.1.27 PIN_FUNCTION
- 7.6.1.28 GPIO_CONFIG
- 7.6.1.29 GPIO_IN
- 7.6.1.30 GPIO_OUT
- 7.6.1
Register Descriptions
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.5.1.4 I2C-Compatible Chip Address
Note:
The device address for the LP875701-Q1 is defined in the Technical Reference Manual (TRM).
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.
Here device address is 1100000Bin
= 60Hex.
Figure 7-17 Example Device Address