ZHCSLV4 December 2020 LP875761-Q1
PRODUCTION DATA
Address: 0x28
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
PG3_SEL[1:0] | PG2_SEL[1:0] | PG1_SEL[1:0] | PG0_SEL[1:0] |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7:6 | PG3_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK3 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |
5:4 | PG2_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK2 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good threshold voltage AND current limit |
3:2 | PG1_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK1 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |
1:0 | PG0_SEL[1:0] | R/W | X | PGOOD signal source control from the BUCK0 regulator 0h = Masked 1h = Power-good-threshold voltage 2h = Reserved, do not use 3h = Power-good-threshold voltage AND current limit |