米6体育平台手机版

ZHCSLV4 December 2020 LP875761-Q1

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机械数据 (封装 | 引脚)

RNF|26

散热焊盘机械数据 (封装 | 引脚)

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zhcslv4_oa

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ +140°C, C_POL = 122 µF/phase, specified V_VANA, V_{VIN_Bx} , V_NRST, V_{VOUT_Bx}, and I_OUT range, unless otherwise noted. Typical values are at T_J = 25°C, V_VANA = V_{VIN_Bx} = 3.7 V, and V_OUT = 1.0 V, unless otherwise noted.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
EXTERNAL COMPONENTS
C_IN	Input filtering capacitance	Connected from VIN_Bx to PGND_Bx	1.9	10		µF
C_OUT	Output filtering capacitance per phase, local		10	22		µF
C_POL	Point-of-load (POL) capacitance per phase			122		µF
C_OUT-TOTAL	Total output capacitance⁽²⁾ (local and POL)	4-phase output	400		1500	µF
ESR_C	ESR of the input and output capacitor	1 MHz ≤ f ≤ 10 MHz		2	10	mΩ
L	Inductor value and tolerance of the inductor			0.33		µH
L	Inductor value and tolerance of the inductor		–30%		30%
DCR_L	Inductor DCR			20		mΩ
BUCK REGULATOR
V_{VIN_Bx}	Input voltage range		2.8		5.5	V
I_OUT	Output current⁽³⁾	4-phase output, V_IN ≥ 3 V			16	A
I_OUT	Output current⁽³⁾	4-phase output, 2.8 V ≤ V_IN < 3 V			12	A
	Input and output voltage difference Minimum voltage between VIN_x and V_OUT to fulfill the electrical characteristics		0.5			V
V_{VOUT_DC}	DC output voltage and accuracy, includes voltage reference, DC load and line regulations, process, and temperature	V_IN= 3.3 V +/- 5% , 5 V +/- 5%, forced PWM mode, forced 4-phase operation, f_SW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled	0.99	1	1.01	V
	Ripple voltage	4-phase output, forced PWM mode, ESR_C < 2 mΩ, L = 0.33 µH		3		mV_p-p
DC_LNR	DC line regulation	I_OUT = I_OUT(max)		0.1		%/V
DC_LDR	DC load regulation in PWM mode	0 A ≤ I_OUT ≤ I_OUT(max)		0.01		%/A
TR_LDSR	Transient load step response in PWM mode	V_IN = 5 V +/- 5% , f_SW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled, forced 4-phase operation, forced PWM mode 4 A ≤ I_OUT ≤ 12 A, t_r = t_f = 1 μs, C_OUT= 22 μF/phase, L = 0.33 μH, C_POL = 122 μF/phase		±18		mV
TR_LDSR	Transient load step response in PWM mode	V_IN = 3.3 V +/- 5% , f_SW= 3 MHz +/- 10% (either through internal or external clock), in case external clock is used: spread-spectrum disabled, forced 4-phase operation, forced PWM mode 4 A ≤ I_OUT ≤ 12 A, t_r = t_f = 1 μs, C_OUT = 22 μF/phase, L = 0.33 μH, C_POL = 122 μF/phase		±19		mV
TR_LNSR	Transient line response	V_{VIN_Bx} stepping 3.15 V ↔ 3.4 V, t_r = t_f = 10 µs, I_OUT = I_OUT(max)		±2		mV
I_{LIM FWD}	Forward current limit for each phase (peak for each switching cycle)	Programmable range	1.5		5	A
		Step size		0.5		A
		Accuracy, V_{VIN_Bx} ≥ 3 V, ILIM ≥ 3 A	–8%	7.5%	20%
		Accuracy, 2.8 V ≤ V_{VIN_Bx} < 3 V, I_LIM ≥ 3. A	–20%	7.5%	20%
I_{LIM NEG}	Negative current limit per phase (peak for each switching cycle)		1.6	2	2.4	A
R_{DS(ON) HS FET}	On-resistance, high-side FET	Each phase, between VIN_Bx and SW_Bx pins, I = 1 A		29	65	mΩ
R_{DS(ON) LS FET}	On-resistance, low-side FET	Each phase, between SW_Bx and PGND_Bx pins, I = 1 A		17	35	mΩ
f_SW	Switching frequency, PWM mode		2.7	3	3.3	MHz
	Current balancing for multiphase outputs	Current mismatch between phases, I_OUT > 1 A/phase			10%
	Start-Up time (soft start)	From ENx to V_OUT = 0.35 V (slew-rate control begins), C_{OUT_TOTAL} = 144 µF/phase		200		µs
	Output voltage slew-rate⁽⁴⁾		3.23	3.8	4.4	mV/µs
	Output pulldown resistance	Regulator disabled	160	230	300	Ω
	Output voltage monitoring for PGOOD pin	Overvoltage monitoring (compared to DC output-voltage level, V_{VOUT_DC})	39	50	64	mV
		Undervoltage monitoring (compared to DC output-voltage level, V_{VOUT_DC})	–53	–40	–29	mV
		Deglitch time during regulator enable PGOOD_SET_DELAY = 0h	4	7	10	µs
		Deglitch time during regulator enable PGOOD_SET_DELAY = 1h	10	11	13	ms
		Deglitch time during operation and after voltage change	4	7	10	µs
	Power-good threshold for interrupt BUCKx_PG_INT, difference from final voltage	Rising ramp voltage, enable or voltage change	–20	–14	–8	mV
		Falling ramp voltage, voltage change	8	14	20	mV
	Power-good threshold for status bit BUCKx_PG_STAT	During operation, status signal is forced to 0h during voltage change	–20	–14	–8	mV
EXTERNAL CLOCK AND PLL
	Nominal frequency of the external input clock		1		24	MHz
	Nominal frequency step size of the external input clock			1		MHz
	Required accuracy from nominal frequency of the external input clock		–30%		10%
	Delay time for missing external clock detection				1.8	µs
	Delay and debounce time for external clock detection				20	µs
	Clock change delay (internal to external) delay from valid clock detection to use of external clock			600		µs
	Cycle-to-cycle PLL output clock jitter			300		ps, p-p
PROTECTION FUNCTIONS
	Thermal warning	Temperature rising, TDIE_WARN_LEVEL = 0h	115	125	135	°C
	Thermal warning	Temperature rising, TDIE_WARN_LEVEL = 1h	127	137	147	°C
	Thermal warning hysteresis			20		°C
	Thermal shutdown	Temperature rising	140	150	160	°C
	Thermal shutdown hysteresis			20		°C
VANA_OVP	VANA overvoltage	Voltage rising	5.6	5.8	6.1	V
VANA_OVP	VANA overvoltage	Voltage falling	5.45	5.73	5.96	V
	VANA overvoltage hysteresis		40			mV
VANA_UVLO	VANA undervoltage lockout	Voltage rising	2.51	2.63	2.75	V
VANA_UVLO	VANA undervoltage lockout	Voltage falling	2.5	2.6	2.7	V
LOAD CURRENT MEASUREMENT
	Current measurement range	Output current for maximum code			20.47	A
	Resolution	LSB		20		mA
	Measurement accuracy	I_OUT > 1 A		<10%
	Measurement time	PWM mode		4		µs
CURRENT CONSUMPTION
	Shutdown current consumption	From VANA and VIN_Bx pins, NRST = 0 V, VANA = VIN_Bx = 3.7 V		1.4		µA
	Standby current consumption	From VANA and VIN_Bx pins, NRST = 1.8 V, VANA = VIN_Bx = 3.7 V, regulators disabled		6.7		µA
	Active current consumption during PWM operation	Total current for forced 4-phase operation, V_IN = 3.3 V		70		mA
	Active current consumption during PWM operation	Total current for forced 4-phase operation, V_IN = 5 V		103		mA
	PLL and clock detector current consumption	Additional current consumption when internal RC oscillator, clock detector and PLL are enabled		2		mA
DIGITAL INPUT SIGNALS: NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
V_IL	Input low level				0.4	V
V_IH	Input high level		1.2			V
V_HYS	Hysteresis of Schmitt trigger inputs		10	77	200	mV
	ENx pulldown resistance	ENx_PD = 1h		500		kΩ
	NRST pulldown resistance	Always present	650	1150	1700	kΩ
DIGITAL OUTPUT SIGNALS: nINT
V_OL	Output low level	I_SOURCE = 2 mA			0.4	V
R_P	External pullup resistor	To VIO supply		10		kΩ
DIGITAL OUTPUT SIGNALS: SDA
V_OL	Output low level	I_SOURCE = 10 mA			0.4	V
DIGITAL OUTPUT SIGNALS: PGOOD, GPIO1, GPIO2, GPIO3
V_OL	Output low level	I_SOURCE = 2 mA			0.4	V
V_OH	Output high level, configured to push-pull	I_SINK = 2 mA	V_VANA – 0.4		V_VANA	V
V_PU	Supply voltage for external pull-up resistor, configured to open-drain				V_VANA	V
R_PU	External pullup resistor, configured to open-drain			10		kΩ
ALL DIGITAL INPUTS
I_LEAK	Input current	All logic inputs over pin voltage range (except NRST)	−1		1	µA

(1) All voltage values are with respect to network ground.

(2) The output voltage slew-rate setting limits the maximum output capacitance.

(3) The maximum output current can be limited by the forward current limit I_{LIM FWD} and by the junction temperature. The power dissipation inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown level if the board and ambient temperatures are high.

(4) Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates. The actual set fixed slew rate value for specific part number is listed in corresponding TRM document.