8.3.3.1 Enabling and Disabling Regulator

The regulator can be enabled when the device is in STANDBY state. There are two ways for enable and disable the regulator:

• Using BUCK0_CTRL1.EN_BUCK0 register bit (BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '0').
• Using EN1/2 control pins (BUCK0_CTRL1.EN_BUCK0 register bit is '1' AND
  BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '1').

If the EN1/2 control pins are used for enable and disable then the delay from the control signal rising edge to startup is set by BUCK0_DELAY.BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to shutdown is set by BUCK0_DELAY.BUCK0_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for EN1/2 signal and not for control with BUCK0_CTRL1.EN_BUCK0 bit. The delay time implemented by EN1/2 has overall +/-10% timing accuracy.

The control of the regulator (with 0 ms delays) is shown in Table 1. The multi-phase regulator is controlled with registers of the master phase.

The following configuration allows the enable/disable control using ENx pin:

• BUCK0_CTRL1.EN_BUCK0 = 1
• BUCK0_CTRL1.EN_PIN_CTRL0 = 1
• BUCK0_CTRL1.EN_ROOF_FLOOR0 = 0
• BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
• The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0

When the ENx pin is low, Table 1 row 3 (or 5) is valid, and the regulator is disabled. By setting ENx pin high, Table 1 row 4 (or 6) is valid, and the regulator is enabled with required voltage.

If the regulator is enabled all the time, and the ENx pin controls selection between two voltage level, the following configuration is used:

• BUCK0_CTRL1.EN_BUCK0 = 1
• BUCK0_CTRL1.EN_PIN_CTRL0 = 1
• BUCK0_CTRL1.EN_ROOF_FLOOR0 = 1
• BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
• The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0

When the ENx pin is low, Table 1 row 7(or 9) is valid, and the regulator is enabled with a voltage defined by BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 1 row 8 (or 10) is valid, and the regulator is enabled with a voltage defined by BUCK0_VOUT.BUCK0_VSET[7:0] bits.

If the regulator is controlled by I²C writings, the BUCK0_CTRL1.EN_PIN_CTRL0 bit is set to 0. The enable/disable is controlled by the BUCK0_CTRL1.EN_BUCK0 bit, and when the regulator is enabled, the output voltage is defined by the BUCK0_VOUT.BUCK0_VSET[7:0] bits. The Table 1 rows 1 and 2 are valid for I²C controlled operation (ENx pins are ignored).

The regulator is enabled by the ENx pin or by I²C writing as shown in Figure 11. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is around 30 mV/μsec during soft-start. When the output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the INT_BUCK_0_1.BUCK0_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using BUCK_0_1_MASK.BUCK0_PG_MASK bit.

The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host can disable those with CONFIG.ENx_PD bits.

Figure 11. Regulator Enable and Disable