7.3.2 Power-Up
The power-up sequence for the LP8758-E0 is as follows:
- VANA (and VIN_Bx) reach minimum recommended levels (V(VANA) > VANAUVLO).
- NRST is set to high level. This initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the LP8758-E0.
- The device enters STANDBY mode.
- The host can change the default register setting by I2C if needed.
- The converter core(s) can be enabled/disabled by ENx pin(s) and by I2C interface.