7.3.4 Device Reset Scenarios

There are three reset methods implemented on the LP8758-E3:

• Software reset with RESET.SW_RESET register bit;
• Reset from low logic level of NRST signal; and
• Undervoltage lockout (UVLO) reset from VANA supply.

A SW-reset occurs when RESET.SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the buck converter cores immediately, resets all the register bits to the default values and OTP bits are loaded (see Figure 12). I²C interface is not reset during software reset.

If VANA supply voltage falls below UVLO threshold level or NRST signal is set low, then all the converter cores are disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage is above UVLO threshold level and NRST signal rises above threshold level an internal power-on reset (POR) occurs. OTP bits are loaded to the registers, and a start-up is initiated according to the register settings.