7.3.3.1 Enabling and Disabling

The buck converter cores can be enabled when the device is in STANDBY or ACTIVE state. There are two ways to enable and disable the buck converter cores:

• Using BUCKx_CTRL1.EN_BUCKx register bit (when BUCKx_CTRL1.EN_PIN_CTRLx register bit is 0).
• Using EN1/2 control pins (BUCKx_CTRL1.EN_BUCKx register bit is 1 and BUCKx_CTRL1.EN_PIN_CTRLx register bit is 1).

If the EN1/2 control pins are used for enable and disable, the delay from the control signal rising edge to start-up is set by BUCKx_DELAY.BUCKx_STARTUP_DELAY[3:0] bits and the delay from control signal falling edge to shutdown is set by BUCKx_DELAY.BUCKx_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for EN1/2 signal and not for control with BUCKx_CTRL1.EN_BUCKx bit. The delay time implemented by EN1/2 has overall ±10% timing accuracy.

The control of the converter cores (with 0 ms delays) is shown in Table 1.

The following buck configuration bit settings allows the device to enable or disable the corresponding buck using the ENx pin:

• BUCKx_CTRL1.EN_BUCKx = 1
• BUCKx_CTRL1.EN_PIN_CTRLx = 1
• BUCKx_CTRL1.EN_ROOF_FLOORx = 0
• BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when the ENx pin is high
• The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx

When the ENx pin is low, Table 1 row 3 (or 5) is valid, and the converter core is disabled. By setting ENx pin high, Table 1 row 4 (or 6) is valid, and the converter core is enabled with required voltage.

If a converter core is enabled all the time, and the ENx pin controls selection between the two voltage levels, then the following configuration is used:

• BUCKx_CTRL1.EN_BUCKx = 1
• BUCKx_CTRL1.EN_PIN_CTRLx = 1
• BUCKx_CTRL1.EN_ROOF_FLOORx = 1
• BUCKx_VOUT.BUCKx_VSET[7:0] = Required voltage when the ENx pin is high
• The enable pin for control is selected with BUCKx_CTRL1.EN_PIN_SELECTx

When the ENx pin is low, Table 1 row 7 (or 9) is valid, and the core is enabled with a voltage defined by BUCKx_FLOOR_VOUT.BUCKx_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 1 row 8 (or 10) is valid, and the core is enabled with a voltage defined by BUCKx_VOUT.BUCKx_VSET[7:0] bits.

If the core is controlled by I²C writings, the BUCKx_CTRL1.EN_PIN_CTRLx bit is set to 0. The enable or disable is controlled by the BUCKx_CTRL1.EN_BUCKx bit, and when the regulator is enabled, the output voltage is defined by the BUCKx_VOUT.BUCKx_VSET[7:0] bits. The Table 1 rows 1 and 2 are valid for I²C controlled operation (ENx pins are ignored).

The buck converter core is enabled by the ENx pin or by I²C writing as shown in Figure 9. The soft-start circuit limits the in-rush current during start-up. Output voltage increase rate is around 5 mV/μsec during soft-start. When the output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the converter core is disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the INT_BUCK_x.BUCKx_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using BUCK_x_MASK.BUCKx_PG_MASK bit.

The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host can disable those with CONFIG.ENx_PD bits.

Figure 9. Converter Core Enable and Disable