米6体育平台手机版

ZHCSNW7 April 2021 LP8758-EA

PRODUCTION DATA

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机械数据 (封装 | 引脚)

YFF|35
- MXBG315

散热焊盘机械数据 (封装 | 引脚)

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ T_J ≤ +125°C, specified V_(VANA), V_IN , V_(NRST), V_OUT and I_OUT range, unless otherwise noted. Typical values are at T_J = 25°C, ƒ_SW = 3 MHz, V_(VANA) = V_IN = 3.7 V and V_OUT = 1 V, unless otherwise noted.⁽¹⁾⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
EXTERNAL COMPONENTS
C_IN	Input filtering capacitance	Connected from VIN_Bx to PGND_Bx	1.9	10		µF
C_OUT	Output filtering capacitance, local	Capacitance per output voltage rail	10	22		µF
C_OUT-TOTAL	Output capacitance, total (local and remote)	Total output capacitance			50	µF
ESR_C	Input and output capacitor ESR	[1-10] MHz		2	10	mΩ
L	Inductor	Inductance of the inductor		0.47		µH
L	Inductor	Inductance of the inductor	–30%		30%
DCR_L	Inductor DCR	TDK, VLS252010HBX-R47M		29		mΩ
BUCK REGULATORS
V_IN	Input voltage range	Voltage between VIN_Bx and ground terminals. VANA must be connected to the same supply as VIN_Bx.	2.5	3.7	5.5	V
V_OUT	Output voltage	Programmable voltage range	0.5	1	3.36	V
		Step size, 0.5 V ≤ V_OUT < 0.73 V		10		mV
		Step size, 0.73 V ≤ V_OUT < 1.4 V		5
		Step size, 1.4 V ≤ V_OUT ≤ 3.36 V		20
I_OUT	Output current	Output current, V_IN ≤ 3 V I_{LIM FWD} programmed to 5 A per phase.			3⁽³⁾	A
		Output current, V_IN > 3 V, V_OUT ≤ 2 V I_{LIM FWD} programmed to 5 A per phase.			4⁽³⁾
		Output current, V_IN > 3 V, V_OUT > 2 V I_{LIM FWD} programmed to 5 A per phase.			3.5⁽³⁾
	Dropout voltage	V_IN – V_OUT	0.7			V
	DC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperature	Force PWM mode	min (–2%, –20 mV)		max (2%, 20 mV)
		PFM mode, the average output voltage level is increased by a maximum of 20 mV.	min (–2%, –20 mV)		max ( 2%, 20 mV) + 20 mV
	Ripple	PWM mode, L = 0.47 µH		10		mV_p-p
	Ripple	PFM mode, L = 0.47 µH		20		mV_p-p
DC_LNR	DC line regulation	I_OUT = 1 A		±0.05		%/V
DC_LDR	DC load regulation in PWM mode	I_OUT from 0 to I_OUT(max)		0.3%
T_LDSR	Transient load step response	I_OUT = 0 A to 2 A, T_R = T_F = 400 ns, PWM mode, C_OUT = 44 µF, L = 0.47 µH		±55		mV
T_LNSR	Transient line response	V_IN stepping 3.3 V ↔ 3.8 V, T_R = T_F = 10 µs, I_OUT = I_OUT(max)		±15		mV
I_{LIM FWD}	Forward current limit (peak for every switching cycle), per phase	Programmable range	2.5		5	A
		Step size		0.5		A
		Accuracy, 3 V ≤ V_IN ≤ 5.5 V, I_{LIM FWD} = 5 A	-5%	7.5%	20%
		Accuracy, 2.5 V ≤ V_IN ≤ 3 V, I_{LIM FWD} = 5 A	-20%	7.5%	20%
I_{LIM NEG}	Negative current limit		1.6	2	2.4	A
R_{DS(ON) HS FET}	On-resistance, high-side FET	Between VIN_Bx and SW_Bx pins (I = 1 A)		40	90	mΩ
R_{DS(ON) LS FET}	On-resistance, low-side FET	Between SW_Bx and PGND_Bx pins (I = 1 A)		33	50	mΩ
	Overshoot during start-up	Slew-rate = 10 mV/µs		< 50		mV
I_PFM-PWM	PFM-to-PWM switch - current threshold⁽⁴⁾			600		mA
I_PWM-PFM	PWM-to-PFM switch - current threshold⁽⁴⁾			240		mA
	Output pulldown resistance	Regulator disabled	150	250	350	Ω
	Powergood threshold for interrupt BUCKx_INT(BUCKx_SC_INT), difference from final voltage	Rising ramp voltage, enable or voltage change	–23	–17	–10	mV
		Falling ramp, voltage change	10	17	23	mV
	Powergood threshold for status signal BUCKx_STAT(BUCKx_PG_STAT)	During operation, status signal is forced to 0 during voltage change.	–23	–17	–10	mV
PROTECTION FEATURES
	Thermal warning	Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 0		125		°C
		Temperature rising, CONFIG(TDIE_WARN_LEVEL) = 1		105
		Hysteresis		15
	Thermal shutdown	Temperature rising		150		°C
	Thermal shutdown	Hysteresis		15		°C
VANA_UVLO	VANA undervoltage lockout	Voltage falling	2.3	2.4	2.5	V
VANA_UVLO	VANA undervoltage lockout	Hysteresis		50		mV
LOAD CURRENT MEASUREMENT
	Current measurement range	Maximum code		20.46		A
	Resolution	LSB		20		mA
	Measurement accuracy	I_OUT ≥ 1 A		< 10%
CURRENT CONSUMPTION
	Shutdown current consumption	V_(NRST) = 0 V		1		µA
	Standby current consumption, converter cores disabled	V_(NRST) = 1.8 V		6		µA
	Active current consumption during PFM operation, one converter core enabled	V_(NRST) = 1.8 V, I_OUT = 0 mA, not switching		55		µA
	Active current consumption during PWM operation, per converter core	V_(NRST) = 1.8 V, I_OUT = 0 mA, L = 0.47 µH		14.5		mA
DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA
V_IL	Input low level				0.4	V
V_IH	Input high level		1.2			V
V_HYS	Hysteresis of Schmitt trigger inputs (SCL, SDA)		10	80	160	mV
	ENx pulldown resistance	ENx_PD = 1	350	500	720	kΩ
	NRST pulldown resistance	Always present	800	1200	1700	kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
V_OL	Output low level	I_SOURCE = 2 mA,			0.4	V
R_P	External pullup resistor for nINT	To VIO supply		10		kΩ
ALL DIGITAL INPUTS
I_LEAK	Input current	All logic inputs over pin voltage range	−1		1	µA

(1) All voltage values are with respect to network ground.

(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.

(3) The maximum output current can be limited by the forward current limit, I_{LIM FWD}. The maximum output current is available with 5-A forward current limit setting.

(4) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependant on the output voltage, input voltage and the magnitude of inductor's ripple current.