An AVS or a DVS voltage value can be configured by the attached MCU after the BUCK regulator is powered up to the default output voltage selected in register BUCKn_VSET1, that loads its default value from NVM. The purpose of the AVS/DVS voltage is to set the BUCK output voltage to enable optimal efficiency and performance of the attached SoC.

All of BUCK regulators in the LP8764-Q1 device support AVS and DVS voltage scaling changes. Once the AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the BUCKn_VSEL register to select the AVS/DVS voltage, the output of the BUCK regulator remains at the AVS/DVS voltage level instead of the default voltage from NVM until one of the following events occur:

• Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY state
• Error that causes the device to execute warm reset
• MCU configures the device to enter the LP STANDBY state if SKIP_LP_STANDBY_EE_READ = 0

Figure 8-12 shows the arbitration scheme for loading the output level of the BUCK regulator from the AVS register using the BUCKn_VSET control registers.

The digital control block automatically updates the OV and UV threshold of the BUCK output voltage monitor during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after a delay calculated by Equation 1.

When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by Equation 1.

In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the OV and UV monitor from the regulator output when the BUCK regulator is enabled and the voltage is rising to the BUCKn_VSETx level. The duration of the mask starts from the time the BUCK regulator is enabled. The BUCK OV monitor output is masked for a fixed delay time of t_{PG_OV_GATE}, that is approximately 115 µs – 128 µs. The UV monitor output is masked for the time duration calculated by Equation 2. The 370-µs additional delay time in the formula includes the start-up delay of the BUCK regulator, the fixed delay after the ramp, and the time for the BIST operation of the OV and UV monitors.

Figure 8-13 and Figure 8-14 are timing diagrams illustrating the voltage change for AVS and DVS enabled BUCK regulators and the corresponding OV and UV monitor threshold changes.