ZHCSQ47 March 2022 LP8764-Q1
PRODUCTION DATA
The default I2C1 7-bit device address of the LP8764-Q1 device is set to a binary value that is described in the User's Guide of the orderable part number of the LP8764-Q1 PMIC, while the two least-significant bits can be changed for alternative page selection listed under Section 8.13.1. The default 7-bit device address for the I2C2 interface, for accessing the watchdog configuration registers and for operating the watchdog in Q&A mode, is described in the User's Guide of the orderable part number of the LP8764-Q1 PMIC.
The I2C-compatible synchronous serial interface provides access to the configurable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode (100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.