The device supports SPI serial-bus interface and it operates as a peripheral device. The MCU in the system acts as the controller device. A single read and write transmission consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order:

• Bits 1-8: ADDR[7:0], Register address
• Bits 9-11: PAGE[2:0], Page address for register
• Bit 12: Read/Write definition, 0 = WRITE, 1 = READ.
• Bits 13-16: RESERVED[4:0], Reserved, use all zeros.
• For Write: Bits 17-24: WDATA[7:0], write data
• For Write with CRC enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits 1-24 sent by the controller device (i.e. the MCU). See Section 8.11.1.
• For Read: Bits 17-24: RDATA[7:0], read data
• For Read with CRC enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits 1-16 sent by the controller device (i.e. the MCU), and bits 17-24, sent by the peripheral device (i.e. the LP8764-Q1). See Section 8.11.1.

In parallel with ADDR[7:0], PAGE[2:0], Read/Write definition and RESERVED[3:0] bits the device sends 16-bit interrupt status using SDO_SPI pin in the following order:

• Bit 1: always 0
• Bits 2-8: status of several interrupts and EN_DRV pin
• Bit 9: always 1
• Bits 10-16: status of several interrupts and EN_DRV pin, with opposite polarity

The status signals are in INT_SPI_STATUS register:

• Bit 8: always 0
• Bit 7: COMM_ADR_ERR_SWINT
• Bit 6: COMM_CRC_ERR_SWINT
• Bit 5: COMM_FRM_ERR_SWINT
• Bit 4: ESM_MCU_PIN_SWINT
• Bit 3: TWARN_SWINT
• Bit 2: WD_SWINT
• Bit 1: EN_DRV_STAT

EN_DRV_STAT bit is showing the live state of the EN_DRV pin, whereas all other status bits are latched in the same way as interrupts indicated with nINT pin. The latched status bits in INT_SPI_STATUS register are cleared by writing 1 to the latched bit. Bits 10-16 are sent for redundancy for bits 2-8 with opposite polarity. Bits 10-16 are always correlating with bits 2-8 and do not change during communication even when the status signal changes.

The embedded CRC filed can be enabled or disabled from the protocol by setting the I2C1_SPI_CRC_EN register bit to '1' - enabled, '0' - disabled. The default of this bit is configurable through the NVM.

The SDO_SPI output is in a high-impedance state when the CS_SPI pin is high. When the CS_SPI pin is low, the SDO_SPI output is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent, the SDO_SPI output is driven accordingly.

The address, page, data, and CRC are transmitted MSB first. The chip-select signal (CS_SPI) must be low during the cycle transmission. The CS_SPI signal resets the interface when it is high, and must be taken high between successive cycles. Data is clocked in on the rising edge of the SCK_SPI clock signal and it is clocked out on the falling edge of SCK_SPI clock signal.

The SPI Timing diagram shows the timing information for these signals.

Figure 8-32 SPI Write Cycle

Figure 8-34 SPI Read Cycle