Section 9.2 shows the output capacitor C_OUT0 and C_OUT1. A ceramic local output capacitor of 22 μF is required for both outputs. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out the current flow from the inductor to the load, whic helps maintain a steady output voltage during transient load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance for good performance is 15 μF for each buck, including the DC voltage roll-off, tolerances, aging, and temperature effects.

The output voltage ripple is caused by charging and discharging the output capacitor, and is also due to its R_ESR. Table 9-5 shows how the R_ESR is frequency dependent (as well as temperature dependent); make sure the value used for selection process is at the part's switching frequency.

POL capacitors can be used to improve load transient performance and to decrease the ripple voltage. A higher output capacitance improves the load step behavior, reduces the output voltage ripple, and decreases the PFM switching frequency. Note: the output capacitor may be the limiting factor in the output voltage ramp, especially for very large (100-μF range) output capacitors. The output voltage might be slower than the programmed ramp rate at voltage transitions for large output capacitors, because of the higher energy stored on the output capacitance. Also, the time required to charge the output capacitor to target value might be longer at start-up. The output voltage is discharged to 0.6 V level using forced-PWM operation at shutdown. This can increase the input voltage if the load current is small and the output capacitor is large compared to the input capacitor. The output capacitor is discharged by the internal discharge resistor when below the 0.6 V level, and more time is required to settle VOUT down with a large capacitor because of the increased time constant.