There are four reset methods implemented on the LP87702-Q1:

• Software reset with the SW_RESET bit in the RESET register
• NRST input signal low
• Undervoltage lockout (UVLO) reset from VANA supply
• Watchdog expiration (depending on the watchdog settings)

A SW reset occurs when the SW_RESET bit is set to 1. The bit is automatically cleared after writing. Figure 8-14shows how this event disables all the converters immediately, drives GPO signals low, resets all the register bits to the default values and the OTP bits are loaded. I²C interface is not reset during a software reset. The host must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.

If VANA supply voltage falls below the UVLO threshold level or the NRST signal is set low, then all the converters are disabled immediately, the GPOx signals are driven low, and all the register bits are reset to the default values. When the VANA supply voltage rises above the UVLO threshold level and the NRST signal rises above the threshold level, the OTP bits are loaded to the registers and a start-up is initiated according to the register settings. The host must wait at least 1.2 ms before reading or writing to the I2C interface.

Depending on the watchdog settings, the watchdog expiration can reset the device to the OTP default values.