8.3.1.1 LED PWM Clock Generation With VSYNC

Unsynchronized LCD line scanning and LED backlight ripple may cause a “waterfall” effect. Synchronizating LED output PWM frequency with video processor or timing controller VSYNC/HSYNC signal can reduce this effect.

The PLL can be used for generating required PWM generation clock from the VSYNC signal. This ensures that the LED output PWM remains synchronized to the VSYNC signal, and there is no clock variation between the LCD display video update and the LED backlight output frequency. If PWM_COUNTER_RESET = 1, the VSYNC signal rising edge restartsthe PWM generation, ensuring there is no clock drifting. The slow divider is intended for LED PWM frequency synchronization with an external VSYNC. An external filter connected to the FILTER pin must be used only if a slow divider is enabled — otherwise the LP8860-Q1 uses internal compensation.

The ƒ_OUT of the PLL must be chosen in the 5-MHz to 40-MHz range. If VSYNC is enabled, the signal must be active before VDDIO/EN is set high and present whenever VDDIO/EN is high.

Figure 9. PLL Clock Generation