8.3.6 Boost Controller

The LP8860-Q1 boost controller generates a 16-V to 48-V supply voltage for the LEDs. Output voltage can be increased by an external resistive voltage divider connected to the FB pin, but voltage lower than 16 V is not supported.

The output voltage can be controlled either with EEPROM register bits <BOOST_INITIAL_VOLTAGE[5:0]>, or automatic adaptive boost control can be used. During start-up the output voltage is ramped to default start-up voltage <BOOST_INITIAL_VOLTAGE[5:0]> where it then adapts to the required voltage based on LED output headroom voltage (if adaptive mode has been enabled in EEPROM). Initial voltage for adaptive voltage control mode must be higher than LED string voltage — otherwise the system may generate a boost overvoltage fault during VDDIO/EN pin toggling if the output boost capacitor is not discharged below the initial voltage before the next boost start-up. A different option is to set <MASK_BOOST_OVP_STATUS> bit high to prevent a boost overvoltage fault.

The converter is a magnetic switching PWM mode DC-DC converter with a current limit. The topology of the magnetic boost converter is called Current Programmed Mode (CPM) control, where the inductor current is measured and controlled with the feedback. Switching frequency is selectable from 100 kHz and 2.2 MHz with EEPROM bits <BOOST_FREQ_SEL[2:0]>. In most cases lower frequency has the highest system efficiency.

In adaptive mode the boost output voltage is adjusted automatically based on LED current sink headroom voltage. Boost output voltage control step size is, in this case, 125 mV to ensure as small as possible current sink headroom and high efficiency. The adaptive mode is enabled with the <EN_ADAP EEPROM> bit. If boost is started with adaptive mode enabled, then the initial boost output voltage value is defined with the <BOOST_INITIAL_VOLTAGE[5:0]> EEPROM register bits in order to eliminate long output voltage iteration time when boost is started after VDDIO/EN toggling or power-on reset.

Boost can be clocked by an external SYNC signal (100 kHz to 2.2 MHz); minimum pulse length for the signal is 200 ns. If an external SYNC disappears, boost uses internal frequency defined by <BOOST_FREQ_SEL[2:0]> EEPROM bits. The boost frequency with external SYNC and EEPROM bits-defined frequency need to be close to each other; maximum frequency mismatch is ±25%. The boost controller has optional spread-spectrum switching operation (±3% from central frequency, 1.875-kHz modulation frequency) which reduces spectrum spikes around the switching frequency and its harmonic frequencies.

Further EMI reduction can be achieved by limiting the rise and fall times of the FET with an additional external resistor on the GD pin.

The boost gate driver is powered directly from VDD voltage or from the charge pump which multiplies V_DD voltage by 2. If the charge pump is disabled, the VDD and CPUMP pins must be tied together.

Figure 21. Boost Converter Topology