ZHCSCK8G May   2014  – October 2017 LP8860-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     系统效率
  4. 4 修订历史记录
  5. 5 器件比较表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Current Sinks Electrical Characteristics
    7. 7.7  Boost Converter Characteristics
    8. 7.8  Logic Interface Characteristics
    9. 7.9  VIN Undervoltage Protection (VIN_UVLO)
    10. 7.10 VDD Undervoltage Protection (VDD_UVLO)
    11. 7.11 VIN Overvoltage Protection (VIN_OVP)
    12. 7.12 VIN Overcurrent Protection (VIN_OCP)
    13. 7.13 Power-Line FET Control Electrical Characteristics
    14. 7.14 External Temp Sensor Control Electrical Characteristics
    15. 7.15 I2C Serial Bus Timing Parameters (SDA, SCLK)
    16. 7.16 SPI Timing Requirements
    17. 7.17 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Boost Controller
      2. 8.1.2 LED Output Configurations
      3. 8.1.3 Display Mode
      4. 8.1.4 Cluster Mode
      5. 8.1.5 Hybrid Dimming
      6. 8.1.6 Charge Pump and Square Waveform (SQW) Output
      7. 8.1.7 Power-Line FET
      8. 8.1.8 Protection Features
      9. 8.1.9 Advanced Thermal Protection Features
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Generation
        1. 8.3.1.1 LED PWM Clock Generation With VSYNC
        2. 8.3.1.2 LED PWM Frequency and Resolution
      2. 8.3.2 Brightness Control (Display Mode)
        1. 8.3.2.1 PWM Input Duty Cycle Based Control
        2. 8.3.2.2 Brightness Register Control
        3. 8.3.2.3 PWM Input Duty × Brightness Register
        4. 8.3.2.4 PWM-Input Direct Control
        5. 8.3.2.5 Brightness Slope
        6. 8.3.2.6 LED Dimming Methods
        7. 8.3.2.7 PWM Calculation Data Flow for Display Mode
      3. 8.3.3 LED Output Modes and Phase Shift PWM (PSPWM) Scheme
      4. 8.3.4 LED Current Setting
      5. 8.3.5 Cluster Mode
      6. 8.3.6 Boost Controller
      7. 8.3.7 Charge Pump
      8. 8.3.8 Powerline Control FET
      9. 8.3.9 Protection and Fault Detection Modes
        1. 8.3.9.1 LED Fault Comparators and Adaptive Boost Control
        2. 8.3.9.2 LED Current Dimming With Internal Temperature Sensor
        3. 8.3.9.3 LED Current Limitation With External NTC Sensor
        4. 8.3.9.4 LED Current Dimming With External NTC Sensor
        5. 8.3.9.5 Protection Feature and Fault Summary
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Fault Recovery State
      4. 8.4.4 Start-Up and Shutdown Sequences
    5. 8.5 Programming
      1. 8.5.1 EEPROM
      2. 8.5.2 Serial Interface
        1. 8.5.2.1 SPI Interface
        2. 8.5.2.2 I2C Serial Bus Interface
          1. 8.5.2.2.1 Interface Bus Overview
          2. 8.5.2.2.2 Data Transactions
          3. 8.5.2.2.3 Acknowledge Cycle
          4. 8.5.2.2.4 Acknowledge After Every Byte Rule
          5. 8.5.2.2.5 Addressing Transfer Formats
          6. 8.5.2.2.6 Control Register Write Cycle
          7. 8.5.2.2.7 Control Register Read Cycle
    6. 8.6 Register Maps
      1. 8.6.1 Register Bit Explanations
        1. 8.6.1.1  Display/Cluster1 Brightness Control MSB
        2. 8.6.1.2  Display/Cluster1 Brightness Control LSB
        3. 8.6.1.3  Display/Cluster1 Output Current MSB
        4. 8.6.1.4  Display/Cluster1 Output Current LSB
        5. 8.6.1.5  Cluster2 Brightness Control MSB
        6. 8.6.1.6  Cluster2 Brightness Control LSB
        7. 8.6.1.7  Cluster2 Output Current
        8. 8.6.1.8  Cluster3 Brightness Control MSB
        9. 8.6.1.9  Cluster3 Brightness Control LSB
        10. 8.6.1.10 Cluster3 Output Current
        11. 8.6.1.11 Cluster4 Brightness Control MSB
        12. 8.6.1.12 Cluster4 Brightness Control LSB
        13. 8.6.1.13 Cluster4 Output Current
        14. 8.6.1.14 Configuration
        15. 8.6.1.15 Status
        16. 8.6.1.16 Fault
        17. 8.6.1.17 LED Fault
        18. 8.6.1.18 Fault Clear
        19. 8.6.1.19 Identification
        20. 8.6.1.20 Temp MSB
        21. 8.6.1.21 Temp LSB
        22. 8.6.1.22 Display LED Current MSB
        23. 8.6.1.23 Display LED Current LSB
        24. 8.6.1.24 Display LED PWM MSB
        25. 8.6.1.25 Display LED PWM LSB
        26. 8.6.1.26 EEPROM Control
        27. 8.6.1.27 EEPROM Unlock Code
      2. 8.6.2 EEPROM Bit Explanations
        1. 8.6.2.1  EEPROM Register 0
        2. 8.6.2.2  EEPROM Register 1
        3. 8.6.2.3  EEPROM Register 2
        4. 8.6.2.4  EEPROM Register 3
        5. 8.6.2.5  EEPROM Register 4
        6. 8.6.2.6  EEPROM Register 5
        7. 8.6.2.7  EEPROM Register 6
        8. 8.6.2.8  EEPROM Register 7
        9. 8.6.2.9  EEPROM Register 8
        10. 8.6.2.10 EEPROM Register 9
        11. 8.6.2.11 EEPROM Register 10
        12. 8.6.2.12 EEPROM Register 11
        13. 8.6.2.13 EEPROM Register 12
        14. 8.6.2.14 EEPROM Register 13
        15. 8.6.2.15 EEPROM Register 14
        16. 8.6.2.16 EEPROM Register 15
        17. 8.6.2.17 EEPROM Register 16
        18. 8.6.2.18 EEPROM Register 17
        19. 8.6.2.19 EEPROM Register 18
        20. 8.6.2.20 EEPROM Register 19
        21. 8.6.2.21 EEPROM Register 20
        22. 8.6.2.22 EEPROM Register 21
        23. 8.6.2.23 EEPROM Register 22
        24. 8.6.2.24 EEPROM Register 23
        25. 8.6.2.25 EEPROM Register 24
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application for Display Backlight
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Inductor Selection
          2. 9.2.1.2.2  Output Capacitor Selection
          3. 9.2.1.2.3  Input Capacitor Selection
          4. 9.2.1.2.4  Charge Pump Output Capacitor
          5. 9.2.1.2.5  Charge Pump Flying Capacitor
          6. 9.2.1.2.6  Diode
          7. 9.2.1.2.7  Boost Converter Transistor
          8. 9.2.1.2.8  Boost Sense Resistor
          9. 9.2.1.2.9  Power Line Transistor
          10. 9.2.1.2.10 Input Current Sense Resistor
          11. 9.2.1.2.11 Filter Component Values
            1. 9.2.1.2.11.1 Critical Components for Design
        3. 9.2.1.3 Application Performance Plots
      2. 9.2.2 Low VDD Voltage and Combined Output Mode Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Performance Plots
      3. 9.2.3 High Output Voltage Application
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Performance Plots
      4. 9.2.4 High Output Current Application
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Performance Plots
      5. 9.2.5 Three-Channel Configuration Without Serial Interface
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
        3. 9.2.5.3 Application Performance Plots
      6. 9.2.6 Solution With Minimum External Components
        1. 9.2.6.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • VFP|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.8 Powerline Control FET

The power-line FET limits peak current from the power line during start-up and allows the boost and LED strings to be disconnected during a fault condition, when device is in fault recovery state.

The power-line control block has VSENSE_P and VSENSE_N pins for sensing input current and a shutdown SD pin for driving the gate of the power-line FET. The power-line FET is opened when the LP8860-Q1 is enabled by VDDIO/EN signal and VIN is greater than VGS in steady state (when pFET is used as a power-line FET). A power-line pFET must be chosen with minimal VGS in steady state. Gate current is defined by the <PL_SD_SINK_LEVEL[1:0]> EEPROM bits.

LP8860-Q1 powerline_control_FET_snvsa21.gifFigure 26. Power-line FET Control

During a shutdown state the LP8860-Q1 closes the power-line FET and prevents possible boost and LED leakage. Sense pins are used to detect overcurrent. Power-line FET is closed when an OCP fault occurs. A VIN OCP is indicated with PL_FET_FAULT bit. The power-line FET closes with all faults, followed by entering to a recovery state.

When it is not possible to choose a pFET with the necessary characteristics, a schematic with nFET can be used (see Charge Pump section, Figure 25); the <NMOS_PLFET_EN EEPROM> bit must be set accordingly. In this case the SD pin provides current to shut down the power-line nFET during fault condition.

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