ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
The EN/VDDIO pin enables the logic and analog blocks. The device goes through the start-up sequence where EEPROM context is loaded to the registers, the power-line FET is enabled during soft start, and boost starts during boost start-time. In this mode I2C and SPI communication are available after soft start, and register settings can be changed.