8.5.1 EEPROM

EEPROM memory stores various parameters for chip control. The 200-bit EEPROM memory is organized as 25 × 8 bits. The EEPROM structure consists of a register front-end and the non-volatile memory (NVM). Register data can be read and written through the I²C/SPI serial interface. EEPROM must be burned with the new data; otherwise, data disappears after power-on reset or VDDIO/EN cycling. PWM outputs and PLL must be disabled when writing to EEPROM registers or burning EEPROM (<DISP_CL1_BRT[15:0]> = 0, <CL2_BRT[12:0]> = 0, <CL3_BRT[12:0]> = 0, <CL2_BRT[12:0]> = 0, <EN_PLL> = 0). To read and program EEPROM NVM separate commands need to be sent. Erase and program voltages are generated internally; no other voltages other than the normal VDD voltage is required. A complete EEPROM memory map is shown in the Table 23.

The user must make sure that VDD power is on, and the VDDIO/EN pin is kept high, during the whole programming/burn sequence to avoid memory corruption.

Figure 44. EEPROM and Register Configuration

EEPROM has protection against accidental writes. EEPROM access can be unlocked by writing a pass code to the EEPROM_UNLOCK register. It unlocks the EEPROM Control register EEPROM_CNTRL and all EEPROM registers. Lock is enabled again by writing any other code to the EEPROM_UNLOCK register (for example, 0x00 enables the lock any time).

EEPROM is used as fixed product-configuration storage, to be set or programmed during production before normal operation. EEPROM can be reprogrammed for evaluation purposes up to 1000 cycles. Data-retention lifetime for factory-programmed content is 10 years, minimum. For more details regarding EEPROM options, see TI Application Note Selecting the Correct LP8860-Q1 EEPROM Version (SNVA757).