8.5.2.1 SPI Interface

The LP8860-Q1 is compatible with SPI serial-bus specification, and it operates as a slave. The transmission consists of 16-bit write and read cycles. One cycle consists of 7 address bits, 1 read/write (R/W) bit, and 8 data bits. The R/W bit high state defines a write cycle and low defines a read cycle. MISO output is normally in a high-impedance state. When the slave select NSS for LP8680 is active (that is, low), MISO output is pulled low for both read and write operations, except for the period when Data is sent out during a read cycle. The Address and Data are transmitted MSB first. The Slave Select signal NSS must be low during the Cycle transmission. NSS resets the interface when high, and it has to be taken high between successive cycles. Data is clocked in on the rising edge of the SCLK clock signal, while data is clocked out on the falling edge of SCLK.

Figure 45. SPI Write Cycle

Figure 46. SPI Read Cycle