ZHCSCK8G May 2014 – October 2017 LP8860-Q1
PRODUCTION DATA.
Each device on the bus has a unique slave address. The LP8860-Q1 operates as a slave device with 7-bit address combined with data direction bit. Default slave address is 2Dh as 7-bit or 5Ah for write and 5Bh for read in 8-bit format.
Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address — the eighth bit. When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1:read, 0:write), the device acts as a transmitter or a receiver.