The number of brightness steps when using LED output PWM dimming is equal to the 20MHz oscillator frequency divided by the LED PWM frequency (set by PWM_FSET resistor). The PWM duty cycle dither is a function the LP8866-Q1 uses to increase the number of brightness dimming steps beyond this oscillator clock limitation. The dither function modulates the LED driver output duty cycle over time to create more possible average brightness levels. The DITHER_SELECT[3:0] register bits control the level of dither, disabled, 1, 2, 3 or 4 bits using the I2C interface. By default the dither is disabled.

When the 1-bit dither is selected, to support higher brightness resolution, the width of every second PWM pulse could be increased by one LSB (one 20MHz clock period). When the 3-bit dither is selected, within a sequence of 8 PWM periods the number of pulses with increased length varies depending on the dither value: dither value 000 - all 8 pulses at default length; 001 - one of the 8 pulses is longer; 010 - two of the 8 pulses are longer, and so forth, until at 111 - seven of the 8 pulses have increased length. Figure 6-14 shows one example of PWM output dither.

Figure 6-14 PWM Dither Example

The dither block also helps in low brightness scenario when dimming ratio is limited by LED PWM output frequency and the LED output pulse is less than the minimum pulse width (200ns). In such scenario, the dither block will skip some of the PWM pulses to reduce the brightness further, enabling high dimming ratio. The end result is that the LED PWM frequency is reduced as more and more minimum pulses are skipped or dithered out. At the same time, dither block will also guarantee that the minimum LED PWM frequency is not less than 152Hz to ensure no brightness flickering. Figure 6-15 shows how the dither works in low brightness scenario.

Figure 6-15 Minimum Brightness Dither Example