11.1 Layout Guidelines

Figure 28 is a layout recommendation for LP886x-Q1 used to demonstrate the principles of a good layout. This layout can be adapted to the actual application layout if or where possible. It is important that all boost components are close to the chip, and the high current traces must be wide enough. By placing boost components on one side of the chip it is easy to keep the ground plane intact below the high current paths. This way other chip pins can be routed more easily without splitting the ground plane. Bypass LDO capacitor must be placed as close as possible to the device.

Here are some main points to help the PCB layout work:

• Current loops need to be minimized:
  • For low frequency the minimal current loop can be achieved by placing the boost components as close as possible to the SW and PGND pins. Input and output capacitor grounds must be close to each other to minimize current loop size.
  • Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact under the current traces. High-frequency return currents find a route with minimum impedance, which is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when return current flows just under the positive current route in the ground plane, if the ground plane is intact under the route. To minimize the current loop for high frequencies:
    • Inductor's pin in SW node needs to be as near as possible to chip's SW pin
    • Put a small capacitor as near as possible to the diode's pin in boost output node and arrange vias to PGND plane close to the capacitor's GND pin.
• Use separate power and noise-free grounds. PGND is used for boost converter return current and noise-free ground is used for more sensitive signals, such as LDO bypass capacitor grounding as well as grounding the GND pin of the device.
• Boost output feedback voltage to LEDs must be taken out after the output capacitors, not straight from the diode cathode.
• Place LDO 1-µF bypass capacitor as close as possible to the LDO pin.
• Input and output capacitors require strong grounding (wide traces, many vias to GND plane).