The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with low on-state resistance, R_DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_DS(on) of a MOSFET, the higher the gate charge and output charge (Q_G and Q_OSS respectively), and vice versa. As a result, the product R_DS(on) × Q_G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection in a LV5144 application are as follows:

• R_DS(on) at V_GS = 7.5 V
• Drain-source voltage rating, BV_DSS, typically 60 V, 80 V, or 100 V, depending on maximum input voltage
• Gate charge parameters at V_GS = 7.5 V
• Output charge, Q_OSS, at the relevant input voltage
• Body diode reverse recovery charge, Q_RR
• Gate threshold voltage, V_GS(th), derived from the Miller plateau evident in the Q_G versus V_GS plot in the MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 5 V, the 7.5-V gate drive amplitude of the LV5144 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-through when off.

The MOSFET-related power losses are summarized by the equations presented in Table 9-1, where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LV5144 Quickstart Calculator to assist with power loss calculations.

Table 9-1 Buck Regulator MOSFET Power Losses

POWER LOSS MODE	HIGH-SIDE MOSFET	LOW-SIDE MOSFET
MOSFET conduction(2)(3)
MOSFET switching		Negligible
MOSFET gate drive(1)
MOSFET output charge(4)
Body diode conduction	N/A
Body diode reverse recovery(5)

The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the transition deadtimes. The LV5144, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low R_DS(on). In cases where the conduction loss is too high or the target R_DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery. The LV5144 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.