Figure 9-34 shows an example PCB layout based on the LV5144-Q1-EVM12V design. The power component connections are made on the top layer with wide, copper-filled polygon areas. The SW connection from the power MOSFETs to the inductor is purposely kept at minimum area to reduce radiated EMI. A power ground plane is placed on layer 2 with 6 mil (0.15 mm) spacing to the top layer, see Figure 9-35. As a result, the buck regulator hot loop has a small effective area based on this tightly-coupled GND plane directly underneath the MOSFETs.

The LV5144 controller is located close to the gate terminals of the MOSFETs such that the gate drive traces are routed short and direct. Refer to the LV5144-Q1-EVM12V Evaluation Module User's Guide for more detail.

Figure 9-34 LV5144 Controller PCB Layout (Viewed From Top)

Note: See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout application brief for more detail.

Figure 9-35 PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing