6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) |
2500 |
V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) |
1500 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.6 Electrical Characteristics—Output Switch
VCC = 5 V, TA = full operating range (unless otherwise noted) (see block diagram)(1)
PARAMETER |
TEST CONDITIONS |
TA |
MIN |
TYP |
MAX |
UNIT |
VCE(sat) |
Saturation voltage – Darlington connection |
ISW = 1 A, pins 1 and 8 connected |
Full range |
|
1 |
1.3 |
V |
VCE(sat) |
Saturation voltage – non-Darlington connection(2) |
ISW = 1 A, RPIN8 = 82 Ω to VCC, forced β ∼ 20 |
Full range |
|
0.45 |
0.7 |
V |
hFE |
DC current gain |
ISW = 1 A, VCE = 5 V |
25°C |
50 |
75 |
|
— |
IC(off) |
Collector off-state current |
VCE = 40 V |
Full range |
|
0.01 |
100 |
μA |
(1) Low duty-cycle pulse testing is used to maintain junction temperature as close to ambient temperature as possible.
(2) In the non-Darlington configuration, if the output switch is driven into hard saturation at low switch currents (≤300 mA) and high driver currents (≥30 mA), it may take up to 2 μs for the switch to come out of saturation. This condition effectively shortens the off time at frequencies ≥30 kHz, becoming magnified as temperature increases. The following output drive condition is recommended in the non-Darlington configuration:
Forced β of output switch = IC,SW / (IC,driver – 7 mA) ≥ 10, where ∼7 mA is required by the 100-Ω resistor in the emitter of the driver to forward bias the Vbe of the switch.