ZHCSSV1 august   2023 MCF8316C-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings Auto
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Motor Control Input Sources
        1. 7.3.8.1 Analog-Mode Motor Control
        2. 7.3.8.2 PWM-Mode Motor Control
        3. 7.3.8.3 I2C-based Motor Control
        4. 7.3.8.4 Frequency-Mode Motor Control
        5. 7.3.8.5 Input Reference Profiles
          1. 7.3.8.5.1 Linear Reference Profiles
          2. 7.3.8.5.2 Staircase Speed Profile
          3. 7.3.8.5.3 Forward-Reverse Speed Profile
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open Loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Torque Mode
        5. 7.3.11.5 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Active Braking
      16. 7.3.16 Output PWM Switching Frequency
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Low-Side Braking
        3. 7.3.19.3 High-Side Braking
        4. 7.3.19.4 Active Spin-Down
        5. 7.3.19.5 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG during Open and Closed Loop States
        3. 7.3.20.3 FG during Fault and Idle States
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Under Voltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.22.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.22.10 FET Thermal Warning (OTW)
        11. 7.3.22.11 FET Thermal Shutdown (TSD_FET)
        12. 7.3.22.12 Motor Lock (MTR_LCK)
          1. 7.3.22.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.22.13 Motor Lock Detection
          1. 7.3.22.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.13.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.22.14 MPET Faults
        15. 7.3.22.15 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Anti voltage surge (AVS)
        6. 8.2.1.6 Real time variable tracking using DACOUT
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 支持资源
    2. 11.2 Trademarks
    3. 11.3 静电放电警告
    4. 11.4 术语表
  13. 12Mechanical, Packaging, and Orderable Information

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7.6.2.3 I2C Read Transaction

MCF8316C-Q1 read transaction over I2C involves the following sequence (see Figure 7-55).

  1. I2C Start condition from the controller to initiate the transaction.
  2. Start is followed by the I2C target ID byte, made up of 7-bit target ID along with the R/W bit set to 0b. ACK (in yellow box) indicates that MCF8316C-Q1 has processed the received target ID which has matched with it's I2C target ID and therefore will proceed with this transaction. If target ID received does not match with the I2C ID of MCF8316C-Q1, then the transaction is ignored and no ACK is sent by MCF8316C-Q1.
  3. The target ID byte is followed by the 24-bit control word sent one byte at a time. Bit 23 in the control word is set to 1b as it is a read transaction. ACK (in blue boxes) correspond to acknowledgements sent by MCF8316C-Q1 to the controller that the previous byte (of control word) has been received and next byte can be sent.
  4. The control word is followed by a Repeated Start (RS, start without a preceding stop) or normal Start (P followed by S) to initiate the data (to be read back) transfer from MCF8316C-Q1 to I2C controller. RS or S is followed by the 7-bit target ID along with R/W bit set to 1b to initiate the read transaction. MCF8316C-Q1 sends an ACK (in grey box after RS) to the controller to acknowledge the receipt of read transaction request.
  5. Post acknowledgement of read transaction request, MCF8316C-Q1 sends the data bytes on SDA one byte at a time. The number of data bytes sent by MCF8316C-Q1 depends on the DLEN field in the control word.
    1. While sending data bytes, the LSB byte is sent first. Refer the examples in Section 7.6.2.4 for more details.
    2. 16-bit/32-bit Read – The data from the address mentioned in control word is sent back to the controller.
    3. 64-bit Read – 64-bit is treated as two successive 32-bit reads. The address mentioned in control word is taken as Addr_1. Addr_2 is internally calculated by MCF8316C-Q1 by incrementing Addr_1 by 0x2. A total of 8 data bytes are sent by MCF8316C-Q1. The first 4 bytes (sent in LSB first) are read from Addr_1 and the next 4 bytes are read from Addr_2.
    4. ACK in orange boxes correspond to acknowledgements sent by the controller to MCF8316C-Q1 that the previous byte has been received and next byte can be sent.
  6. If CRC is enabled in the control word, then MCF8316C-Q1 sends an additional CRC byte at the end. Controller has to read the CRC byte and then send the last ACK (in orange). CRC is calculated for the entire packet (Target ID + W bit, Control Word, Target ID + R bit, Data Bytes).
  7. I2C Stop condition from the controller to terminate the transaction.
GUID-D552388B-F165-4F1F-98AE-1584A43DE42E-low.svgFigure 7-55 I2C Read Transaction Sequence
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