ZHCSGF0D July   2017  – October 2019 MCP6291 , MCP6292 , MCP6294

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      低侧电机控制
      2.      小信号过冲与负载电容间的关系
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: MCP6921
    2.     Pin Functions: MCP6292
    3.     Pin Functions: MCP6294
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: MCP6291
    5. 7.5 Thermal Information: MCP6292
    6. 7.6 Thermal Information: MCP6294
    7. 7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Rail-to-Rail Output
      3. 8.3.3 Overload Recovery
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.4 V to 5.5 V

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±0.3 ±3 mV
VS = 5 V, TA = –40°C to 125°C ±5
dVOS/dT Drift VS = 5 V, TA = –40°C to 125°C ±1.1 µV/°C
PSRR Power-supply rejection ratio VS = 2.4 V – 5.5 V, VCM = (V–) ±7 µV/V
Channel separation, DC At DC 100 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range VS = 2.4 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C 		80 103 dB
VS = 5.5 V
VCM = –0.1 V to 5.6 V
TA = –40°C to 125°C 		57 87
VS = 2.4 V
(V–) – 0.1 V < VCM < (V+) – 1.4 V
TA = –40°C to 125°C 		88
VS = 2.4 V
VCM = –0.1 V to 1.9 V
TA = –40°C to 125°C		 81
INPUT BIAS CURRENT
IB Input bias current ±1 pA
IOS Input offset current ±0.05 pA
NOISE
En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 4.77 µVPP
en Input voltage noise density VS = 5 V, f = 10 kHz, RL = 10 kΩ 8.7 nV/√Hz
VS = 5 V, f = 1 kHz, RL = 10 kΩ 16
in Input current noise density f = 1 kHz 10 fA/√Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 2.4 V
(V–) + 0.04 V < VO < (V+) – 0.04 V
RL = 10 kΩ		 100 dB
VS = 5.5 V
(V–) + 0.05 V < VO < (V+) – 0.05 V
RL = 10 kΩ		 104 130
VS = 2.4 V
(V–) + 0.06 V < VO < (V+) – 0.06 V
RL = 2 kΩ		 100
VS = 5.5 V
(V–) + 0.15 V < VO < (V+) – 0.15 V
RL = 2 kΩ		 130
FREQUENCY RESPONSE
GBP Gain bandwidth product VS = 5 V, G = 1 10 MHz
φm Phase margin VS = 5 V, G = 1 55 °
SR Slew rate VS = 5 V, G = 1 6.5 V/µs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = 1
CL = 100 pF		 0.5 µs
To 0.01%, VS = 5 V, 2-V step , G = 1
CL = 100 pF		 1
tOR Overload recovery time VS = 5 V
VIN  × gain > VS 		0.2 µs
THD + N Total harmonic distortion + noise(1) VS = 5 V
VO = 1 VRMS
G = 1, f = 1 kHz		 0.0008%
OUTPUT
VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ 15 mV
VS = 5.5 V, RL = 2 kΩ 50
ISC Short-circuit current VS = 5 V ±50 mA
ZO Open-loop output impedance VS = 5 V, f = 10 MHz 100 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA 600 1300 µA
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
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