ZHCSPQ7A december   2022  – april 2023 MCT8315A

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Under Voltage Protection
        7. 7.3.3.7 Buck Over Current Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  Speed Control
        1. 7.3.8.1 Analog Mode Speed Control
        2. 7.3.8.2 PWM Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency Mode Speed Control
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 120o Commutation
          1. 7.3.11.1.1 High-Side Modulation
          2. 7.3.11.1.2 Low-Side Modulation
          3. 7.3.11.1.3 Mixed Modulation
        2. 7.3.11.2 Variable Commutation
        3. 7.3.11.3 Lead Angle Control
        4. 7.3.11.4 Closed loop accelerate
      12. 7.3.12 Speed Loop
      13. 7.3.13 Input Power Regulation
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Fast Start-up (< 50 ms)
        1. 7.3.16.1 BEMF Threshold
        2. 7.3.16.2 Dynamic Degauss
      17. 7.3.17 Fast Deceleration
      18. 7.3.18 Active Demagnetization
        1. 7.3.18.1 Active Demagnetization in action
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 Protections
        1. 7.3.21.1  VM Supply Undervoltage Lockout
        2. 7.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.21.5  Overvoltage Protection (OVP)
        6. 7.3.21.6  Overcurrent Protection (OCP)
          1. 7.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.21.7  Buck Overcurrent Protection
        8. 7.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 7.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 7.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 7.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 7.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 7.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 7.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 7.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 7.3.21.10 Thermal Warning (OTW)
        11. 7.3.21.11 Thermal Shutdown (TSD)
        12. 7.3.21.12 Motor Lock (MTR_LCK)
          1. 7.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 7.3.21.13 Motor Lock Detection
          1. 7.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 7.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 7.3.21.14 SW VM Undervoltage Protection
        15. 7.3.21.15 SW VM Overvoltage Protection
        16. 7.3.21.16 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 DAC outputs
      3. 7.5.3 Current Sense Output
      4. 7.5.4 Oscillator Source
        1. 7.5.4.1 External Clock Source
      5. 7.5.5 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Transaction
        3. 7.6.2.3 I2C Read Transaction
        4. 7.6.2.4 I2C Communication Protocol Packet Examples
        5. 7.6.2.5 I2C Clock Stretching
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Gate_Driver_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Algo_Control Registers
      4. 7.8.4 Device_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 120o and variable commutation
        3. 8.2.1.3 Faster startup time
        4. 8.2.1.4 Setting the BEMF threshold
        5. 8.2.1.5 Maximum speed
        6. 8.2.1.6 Faster deceleration
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 支持资源
    2. 11.2 Trademarks
    3. 11.3 静电放电警告
    4. 11.4 术语表
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

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7.3.21 Protections

The MCT8315A is protected from a host of fault events including motor lock, VM undervoltage, AVDD undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table 7-2 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.

Note:
  1. Actionable faults (latched or retry) are always reported on nFAULT pin (as logic low).
  2. Actionable faults (latched or retry) are reported on ALARM pin (as logic high) when ALARM_PIN_EN is set to 1b.
  3. Report only faults are reported on nFAULT (as logic low) only when ALARM_PIN_EN is set to 0b. When ALARM_PIN_EN is set to 1b, report only faults are reported only on ALARM pin (as logic high) while nFAULT stays high (external pull-up).
  4. Priority order for multi-fault scenarios is latched > slower retry time fault > faster retry time fault > report only fault. For example, if a latched and retry fault happen simultaneously, the device stays latched in fault mode until user issues clear fault command by writing 1b to CLR_FLT. If two retry faults with different retry times happen simultaneously, the device retries only after the longer (slower) retry time lapses.
  5. Recovery refers only to state of FETs (Hi-Z or active) after the fault condition is removed. Automatic indicates that the device automatically recovers (and FETs are active) when retry time lapses after the fault condition is removed. Latched indicates that the device waits for clearing of fault condition (by writing 1b to CLR_FLT bit) to make the FETs active again.
  6. Actionable (latched or retry) faults can take up to 200-ms after fault response (FETs in Hi-Z) to be reported on nFAULT pin (as logic low), ALARM pin (as logic high) and fault status registers.
  7. Latched faults can take up to 200-ms after CLR_FLT command is issued (over I2C) to be cleared.
Table 7-2 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT FETs DIGITAL RECOVERY
VM undervoltage VVM < VUVLO — — Hi-Z Disabled Automatic:
VVM > VUVLO
AVDD undervoltage VAVDD < VAVDD_UV — — Hi-Z Disabled Automatic:
VAVDD > VAVDD_UV
Buck undervoltage
(BUCK_UV)		 VFB_BK < VBK_UV — — Active/Hi-Z Active/Disabled Automatic:
VFB_BK > VBK_UV
Charge pump undervoltage
(VCP_UV)		 VCP < VCPUV — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVCP > VCPUV
Over Voltage Protection
(OVP)		 VVM > VOVP OVP_EN = 0b None Active Active No action
OVP_EN = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVM < VOVP
Over Current Protection
(OCP)		 IPHASE > IOCP OCP_MODE = 00b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
OCP_MODE = 01b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Retry:
tRETRY
OCP_MODE = 10b nFAULT and GATE_DRIVER_FAULT_STATUS register Active Active No action
OCP_MODE = 11b None Active Active No action
Buck Overcurrent Protection
(BUCK_OCP)		 IBK > IBK_OCP — — Hi-Z Disabled Automatic
Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Loss of Sync MTR_LCK_MODE = 0000b or 0001b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MTR_LCK_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0100b or 0101b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 1xx1b None Active Active No action
Cycle by Cycle Current Limit
(CBC_ILIMIT)		 VSOX > CBC_ILIMIT CBC_ILIMIT_MODE = 0000b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Automatic:
Next PWM cycle
CBC_ILIMIT_MODE = 0001b None Recirculation Active Automatic:
Next PWM cycle
CBC_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Automatic:
VSOX < CBC_ILIMIT
CBC_ILIMIT_MODE = 0011b None Recirculation Active Automatic:
VSOX < CBC_ILIMIT
CBC_ILIMIT_MODE = 0100b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
CBC_ILIMIT_MODE = 0101b None Recirculation Active Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
CBC_ILIMIT_MODE= 0110b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
CBC_ILIMIT_MODE = 0111b, 1xxxb None Active Active No action
Lock-Detection Current Limit
(LOCK_ILIMIT)
VSOX > LOCK_ILIMIT LOCK_ILIMIT_MODE = 0000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0001b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0100b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0101b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 1xx1b None Active Active No action
IPD Timeout Fault
(IPD_T1_FAULT and IPD_T2_FAULT)		 IPD TIME > 500ms (approx.), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_EN = 0b — Active Active No action
IPD_TIMEOUT_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
IPD Timeout Fault
(IPD_T1_FAULT and IPD_T2_FAULT)		 IPD TIME > 500ms (approx.), during IPD current ramp up or ramp down — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched: CLR_FLT
IPD Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD pulse IPD_FREQ_FAULT_EN = 0b — Active Active No action
IPD_FREQ_FAULT_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry: tLCK_RETRY
IPD Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD pulse — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched: CLR_FLT
Maximum VM (overvoltage) fault VVM > MAX_VM_MOTOR, if MAX_VM_MOTOR ≠ 000b MAX_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MAX_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM < MAX_VM_MOTOR - 1)-V
Minimum VM (undervoltage) fault VVM < MIN_VM_MOTOR, if MIN_VM_MOTOR ≠ 000b MIN_VM_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MIN_VM_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
(VVM > MIN_VM_MOTOR + 0.5)-V
External Watchdog Watchdog tickle does not arrive before configured time interval when EXT_WDT_EN =1b. Refer Section 7.5.5 EXT_WDT_FAULT_MODE = 0b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
EXT_WDT_FAULT_MODE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Bus Current Limit IVM > BUS_CURRENT_LIMIT. Refer BUS_CURRENT_LIMIT_ENABLE = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed will be restricted to limit DC bus current Active Automatic: Speed restriction is removed when IVM < BUS_CURRENT_LIMIT
Current Loop Saturation Indication of current loop saturation due to lower VVM SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Speed Loop Saturation Indication of speed loop saturation due to lower VVM, lower ILIMIT setting etc., SATURATION_FLAGS_EN = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active; motor speed may not reach speed reference Active Automatic: motor will reach reference operating point upon exiting saturation
Thermal warning
(OTW)		 TJ > TOTW OTW_REP = 0b — Active Active No action
OTW_REP = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Active Active Automatic:
TJ < TOTW – TOTW_HYS
Thermal shutdown
(TSD)		 TJ > TTSD — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
TJ < TTSD – TTSD_HYS
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