The buck regulator implements a pulse frequency modulation (PFM) architecture with peak current mode control. The output voltage of the buck regulator is compared with the internal reference voltage (V_{BK_REF}) which is internally generated depending on the buck-output voltage setting (BUCK_SEL) which constitutes an outer voltage control loop. Depending on the comparator output going high (V_BK < V_{BK_REF}) or low (V_BK > V_{BK_REF}), the high-side power FET of the buck turns on and off respectively. An independent current control loop monitors the current in high-side power FET (I_BK) and turns off the high-side FET when the current becomes higher than the buck current limit (I_{BK_CL}). This implements a current limit control for the buck regulator. Figure 8-7 shows the architecture of the buck and various control/protection loops.