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SLAS421B April 2004 – November 2016 MSP430F423 , MSP430F425 , MSP430F427

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5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Voltage applied at V_CC to V_SS		–0.3	4.1	V
Voltage applied to any pin⁽²⁾		–0.3	V_CC + 0.3	V
Diode current at any device terminal			±2	mA
Storage temperature range, T_stg	Unprogrammed device	–55	150	°C
Storage temperature range, T_stg	Programmed device	–40	85	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to V_SS.The JTAG fuse-blow voltage, V_FB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TDI/TCLK pin when blowing the JTAG fuse.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)

				MIN	NOM	MAX	UNIT
V_CC	Supply voltage during program execution⁽¹⁾ (AV_CC = DV_CC = V_CC)	SD16 disabled		1.8		3.6	V
		SVS enabled, PORON = 1⁽²⁾, SD16 disabled		2.0		3.6
		SD16 enabled or during programming of flash memory		2.7		3.6
V_SS	Supply voltage (AV_SS = DV_SS = V_SS)			0		0	V
T_A	Operating free-air temperature range			–40		85	°C
f_(LFXT1)	LFXT1 crystal frequency⁽³⁾	LF selected, XTS_FLL = 0	Watch crystal		32.768		kHz
		XT1 selected, XTS_FLL = 1	Ceramic resonator	450		8000
		XT1 selected, XTS_FLL = 1	Crystal	1000		8000
f_(System)	Processor frequency (signal MCLK) (also see Figure 5-1)	V_CC = 1.8 V		DC		4.15	MHz
f_(System)	Processor frequency (signal MCLK) (also see Figure 5-1)	V_CC = 3.6 V		DC		8	MHz

(1) TI recommends powering AV_CC and DV_CC from the same source. A maximum difference of 0.3 V between AV_CC and DV_CC can be tolerated during power up and operation.

(2) The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.

(3) In LF mode, the LFXT1 oscillator requires a watch crystal.

MSP430F427 MSP430F425 MSP430F423 frequency_vs_supply_voltage.gif

Figure 5-1 Frequency vs Supply Voltage

5.4 Supply Current Into AV_CC and DV_CC Excluding External Current⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		T_A	V_CC	TYP	MAX	UNIT
I_(AM)	Active mode (AM) f_(MCLK) = f_(SMCLK) = f_(DCO) = 1 MHz, f_(ACLK) = 32768 Hz, XTS_FLL = 0, program executes in flash	–40°C to 85°C	3 V	400	500	µA
I_(LPM0)	Low-power mode 0 or 1 (LPM0 or LPM1)⁽²⁾ f_(MCLK) = f_(SMCLK) = f_(DCO) = 1 MHz, f_(ACLK) = 32768 Hz, XTS_FLL = 0, FN_8 = FN_4 = FN_3 = FN_2 = 0	–40°C to 85°C	3 V	130	150	µA
I_(LPM2)	Low-power mode 2 (LPM2)⁽²⁾	–40°C to 85°C	3 V	10	22	µA
I_(LPM3)	Low-power mode 3 (LPM3) ⁽²⁾	–40°C	3 V	1.5	2.0	µA
		25°C		1.6	2.1
		60°C		1.7	2.2
		85°C		2.0	3.5
I_(LPM4)	Low-power mode 4 (LPM4)⁽²⁾	–40°C	3 V	0.1	0.5	µA
		25°C		0.1	0.5
		85°C		0.8	2.5

(1) All inputs are tied to 0 V or V_CC. Outputs do not source or sink any current. The current consumption in LPM2, LPM3, and LPM4 are measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the SD16 and the SVS module are specified in their respective sections. LPMx currents measured with WDT+ disabled. The currents are characterized with a KDS Daishinku DT-38 (6 pF) crystal.

(2) Current consumption for brownout is included.

Current consumption of active mode versus system frequency:

I_(AM) = I_(AM) [at 1 MHz] × f_(System) [MHz]

Current consumption of active mode versus supply voltage:

I_(AM) = I_(AM) [at 3 V] + 170 µA/V × (V_CC – 3 V)

5.5 Thermal Resistance Characteristics, PM Package (LQFP64)

PARAMETER		VALUE	UNIT
Rθ_JA	Junction-to-ambient thermal resistance, still air⁽¹⁾	55.7	°C/W
Rθ_JC(TOP)	Junction-to-case (top) thermal resistance⁽²⁾	16.7	°C/W
Rθ_JB	Junction-to-board thermal resistance⁽³⁾	27.1	°C/W
Ψ_JB	Junction-to-board thermal characterization parameter	26.8	°C/W
Ψ_JT	Junction-to-top thermal characterization parameter	0.8	°C/W

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

5.6 Schmitt-Trigger Inputs − Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		V_CC	MIN	MAX	UNIT
V_IT+	Positive-going input threshold voltage	3 V	1.5	1.98	V
V_IT-	Negative-going input threshold voltage	3 V	0.9	1.3	V
V_hys	Input voltage hysteresis (V_IT+ - V_IT-)	3 V	0.45	1	V

5.7 Inputs P1.x, P2.x, TAx

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_(int)	External interrupt timing	Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag⁽¹⁾	3 V	1.5		cycle
t_(int)	External interrupt timing		3 V	50		ns
t_(cap)	Timer_A capture timing	TAx	3 V	50		ns
f_(TAext)	Timer_A clock frequency externally applied to pin	TAxCLK, INCLK t_(H) = t_(L)	3 V		10	MHz
f_(TAint)	Timer_A clock frequency	SMCLK or ACLK signal selected	3 V		10	MHz

(1) The external signal sets the interrupt flag every time the minimum t_(int) parameters are met. It may be set even with trigger signals shorter than t_(int). Both the cycle and timing specifications must be met to ensure the flag is set. t_(int) is measured in MCLK cycles.

5.8 Leakage Current − Ports (P1 and P2)⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
I_lkg(P1.x)	Leakage current, Port P1.x	Port 1: V_(P1.x) ⁽²⁾	3 V		±50	nA
I_lkg(P2.x)	Leakage current, Port P2.x	Port 2: V_(P2.x) ⁽²⁾	3 V		±50	nA

(1) The leakage current is measured with V_SS or V_CC applied to the corresponding pins, unless otherwise noted.

(2) The port pin must be selected as input.

5.9 Outputs − Ports (P1 and P2)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
V_OH	High-level output voltage	I_OH(max) = –1.5 mA⁽¹⁾	3 V	V_CC – 0.25	V_CC	V
V_OH	High-level output voltage	I_OH(max) = –6 mA⁽²⁾	3 V	V_CC – 0.6	V_CC	V
V_OL	Low-level output voltage	I_OL(max) = 1.5 mA⁽¹⁾	3 V	V_SS	V_SS + 0.25	V
V_OL	Low-level output voltage	I_OL(max) = 6 mA⁽²⁾	3 V	V_SS	V_SS + 0.6	V

(1) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified voltage drop.

(2) The maximum total current, I_OH(max) and I_OL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified voltage drop.

5.10 Output Frequency

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
f_(Px.y)	Output frequency (1 ≤ × ≤ 2, 0 ≤ y ≤ 7)	C_L = 20 F, I_L = ±1.5 mA, V_CC = 3 V		DC		12	MHz
f_(ACLK),	P1.1/TA0/MCLK, P1.5/TACLK/ACLK/S28	C_L = 20 pF, V_CC = 3 V				12	MHz
f_(MCLK),
f_(SMCLK)
t_(Xdc)	Duty cycle of output frequency	P1.5/TACLK/ACLK/S28, C_L = 20 pF, V_CC = 3 V	f_ACLK = f_LFXT1 = f_XT1	40%		60%
			f_ACLK = f_LFXT1 = f_LF	30%		70%
			f_ACLK = f_LFXT1		50%
		P1.1/TA0/MCLK, C_L = 20 pF, V_CC = 3 V, f_MCLK = f_DCOCLK		50% – 15 ns	50%	50% + 15 ns

5.11 Typical Characteristics – Ports P1 and P2

Figure 5-2 through Figure 5-5 show the typical output currents of Ports P1 and P2. One output loaded at a time.

MSP430F427 MSP430F425 MSP430F423 g_iol_vol_2p2v.gif

Figure 5-2 Typical Low-Level Output Current vs
Low-Level Output Voltage

MSP430F427 MSP430F425 MSP430F423 g_ioh_voh_2p2v.gif

Figure 5-4 Typical High-Level Output Current vs
High-Level Output Voltage

MSP430F427 MSP430F425 MSP430F423 g_iol_vol_3v.gif

Figure 5-3 Typical Low-Level Output Current vs
Low-Level Output Voltage

MSP430F427 MSP430F425 MSP430F423 g_ioh_voh_3v.gif

Figure 5-5 Typical High-Level Output Current vs
High-Level Output Voltage

5.12 Wake-up Time From LPM3

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MAX	UNIT
t_d(LPM3)	Delay time	f = 1 MHz	V_CC = 3 V	6	µs
		f = 2 MHz		6
		f = 3 MHz		6

5.13 RAM

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	MAX	UNIT
V_RAMh		CPU halted⁽¹⁾		1.6		V

(1) This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution should take place during this supply voltage condition.

5.14 LCD

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V₍₃₃₎	Analog voltage	Voltage at R33	V_CC = 3 V	2.5		V_CC + 0.2	V
V₍₂₃₎		Voltage at R23			[V₍₃₃₎ – V₍₀₃₎] × 2/3 + V₍₀₃₎
V₍₁₃₎		Voltage at R13			[V₍₃₃₎ – V₍₀₃₎] × 1/3 + V₍₀₃₎
V₍₃₃₎ – V₍₀₃₎		Voltage at R33 to R03		2.5		V_CC + 0.2
I_(R03)	Input leakage	R03 = V_SS	No load at all segment and common lines, V_CC = 3 V			±20	nA
I_(R13)		R13 = V_CC / 3				±20
I_(R23)		R23 = 2 × V_CC / 3				±20
V_(Sxx0)	Segment line voltage	I_(Sxx) = –3 µA, V_CC = 3 V		V₍₀₃)		V₍₀₃₎ – 0.1	V
V_(Sxx1)				V₍₁₃₎		V₍₁₃₎ – 0.1
V_(Sxx2)				V₍₂₃₎		V₍₂₃₎ – 0.1
V_(Sxx3)				V₍₃₃)		V₍₃₃₎ + 0.1

5.15 USART0⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_(τ)	USART0 deglitch time	V_CC = 3 V, SYNC = 0, UART mode	150	280	500	ns

(1) The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the URXD0 line.

5.16 POR, BOR⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_d(BOR)	Brownout⁽²⁾				2000	µs
V_CC(start)		dV_CC/dt ≤ 3 V/s (see Figure 5-6)		0.7 × V_{(B_IT– )}		V
V_{(B_IT–)}		dV_CC/dt ≤ 3 V/s (see Figure 5-6 through Figure 5-8)			1.71	V
V_{hys(B_IT–)}		dV_CC/dt ≤ 3 V/s (see Figure 5-6)	70	130	180	mV
t_(reset)		Pulse duration needed at RST/NMI pin to accept reset internally, V_CC = 3 V	2			µs

(1) The current consumption of the brownout module is already included in the I_CC current consumption data. The voltage level V_{(B_IT–)} + V_{hys(B_IT–)} ≤ 1.8 V.

(2) During power up, the CPU begins code execution following a period of t_d(BOR)after V_CC = V_{(B_IT–)}+ V_{hys(B_IT–)}. The default FLL+ settings must not be changed until V_CC ≥ V_CC(min), where V_CC(min) is the minimum supply voltage for the desired operating frequency. See the MSP430x4xx Family User's Guide for more information on the brownout and SVS circuit.

MSP430F427 MSP430F425 MSP430F423 por_bor_vs_supply_voltage.gif

Figure 5-6 POR and BOR vs Supply Voltage

MSP430F427 MSP430F425 MSP430F423 por_bor_vccdrop_square.gif

Figure 5-7 V_CC(drop) Level With a Rectangular Voltage Drop to Generate a POR or BOR Signal

MSP430F427 MSP430F425 MSP430F423 por_bor_vccdrop_triangle.gif

Figure 5-8 V_CC(drop) Level With a Triangular Voltage Drop to Generate a POR or BOR Signal

5.17 SVS (Supply Voltage Supervisor and Monitor)⁽³⁾

over recommended operating free-air temperature range (unless otherwise noted) (also see Figure 5-10)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_(SVSR)	dV_CC/dt > 30 V/ms (see Figure 5-9)		5		150	µs
t_(SVSR)	dV_CC/dt ≤ 30 V/ms				2000	µs
t_d(SVSon)	SVS on, switch from VLD = 0 to VLD ≠ 0, V_CC = 3 V		20		150	µs
t_settle	VLD ≠ 0⁽²⁾				12	µs
V_(SVSstart)	VLD ≠ 0, V_CC/dt ≤ 3 V/s (see Figure 5-9)			1.55	1.7	V
V_{hys(SVS_IT–)}	V_CC/dt ≤ 3 V/s (see Figure 5-9)	VLD = 1	70	120	155	mV
	V_CC/dt ≤ 3 V/s (see Figure 5-9)	VLD = 2 to 14	V_{(SVS_IT–)} × 0.004		V_{(SVS_IT–)} × 0.008
	V_CC/dt ≤ 3 V/s (see Figure 5-9), external voltage applied on P2.3	VLD = 15	4.4		10.4	mV
V_{(SVS_IT–)}	V_CC/dt ≤ 3 V/s (see Figure 5-9)	VLD = 1	1.8	1.9	2.05	V
		VLD = 2	1.94	2.1	2.25
		VLD = 3	2.05	2.2	2.37
		VLD = 4	2.14	2.3	2.48
		VLD = 5	2.24	2.4	2.6
		VLD = 6	2.33	2.5	2.71
		VLD = 7	2.46	2.65	2.86
		VLD = 8	2.58	2.8	3
		VLD = 9	2.69	2.9	3.13
		VLD = 10	2.83	3.05	3.29
		VLD = 11	2.94	3.2	3.42
		VLD = 12	3.11	3.35	3.61⁽¹⁾
		VLD = 13	3.24	3.5	3.76⁽¹⁾
		VLD = 14	3.43	3.7⁽¹⁾	3.99⁽¹⁾
	V_CC/dt ≤ 3 V/s (see Figure 5-9), external voltage applied on P2.3	VLD = 15	1.1	1.2	1.3
I_CC(SVS)⁽³⁾	VLD ≠ 0, V_CC = 2.2 V or 3 V			10	15	µA

(1) The recommended operating voltage range is limited to 3.6 V.

(2) t_settleis the settling time that the comparator o/p must have a stable level after VLD is switched from VLD ≠ 0 to a different VLD value between 2 and 15. The overdrive is assumed to be greater than 50 mV.

(3) The current consumption of the SVS module is not included in the I_CC current consumption data.

MSP430F427 MSP430F425 MSP430F423 svs_reset_vs_supply_voltage.gif

Figure 5-9 SVS Reset (SVSR) vs Supply Voltage

MSP430F427 MSP430F425 MSP430F423 svs_vccdrop_square_triangle.gif

Figure 5-10 V_CC(drop) With a Rectangular Voltage Drop and a Triangular Voltage Drop to Generate an SVS Signal

5.18 DCO

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-11 through Figure 5-13)

PARAMETER	TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_(DCOCLK)	N_(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0, f_Crystal = 32.768 kHz	3 V		1		MHz
f_{(DCO = 2)}	FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1	3 V	0.3	0.7	1.3	MHz
f_{(DCO = 27)}	FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1	3 V	2.7	6.1	11.3	MHz
f_{(DCO = 2)}	FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1	3 V	0.8	1.5	2.5	MHz
f_{(DCO = 27)}	FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1	3 V	6.5	12.1	20	MHz
f_{(DCO = 2)}	FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1	3 V	1.3	2.2	3.5	MHz
f_{(DCO = 27)}	FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1	3 V	10.3	17.9	28.5	MHz
f_{(DCO = 2)}	FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1	3 V	2.1	3.4	5.2	MHz
f_{(DCO = 27)}	FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1	3 V	16	26.6	41	MHz
f_{(DCO = 2)}	FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1	3 V	4.2	6.3	9.2	MHz
f_{(DCO = 27)}	FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1	3 V	30	46	70	MHz
S_n	Step size (ratio) between adjacent DCO taps: S_n = f_{DCO(Tap n+1)}/f_{DCO(Tap n)} (see Figure 5-12 for taps 21 to 27)	1 < TAP ≤ 20	1.06		1.11
S_n		TAP = 27	1.07		1.17
D_t	Temperature drift, N_(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0	3 V	–0.2	–0.3	–0.4	%/°C
D_V	Drift with V_CC variation, N_(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0		0	5	15	%/V

MSP430F427 MSP430F425 MSP430F423 dco_freq_supply_temp.gif

Figure 5-11 DCO Frequency vs Supply Voltage (V_CC) and vs Ambient Temperature

MSP430F427 MSP430F425 MSP430F423 dco_tap_step_size.gif

Figure 5-12 DCO Tap Step Size

MSP430F427 MSP430F425 MSP430F423 dco_five_overlapping_ranges.gif

Figure 5-13 Five Overlapping DCO Ranges Controlled by FN_x Bits

5.19 Crystal Oscillator, LFXT1 Oscillator⁽¹⁾ ⁽²⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
C_XIN	Integrated input capacitance⁽⁴⁾	OSCCAPx = 0h	3 V		0		pF
		OSCCAPx = 1h			10
		OSCCAPx = 2h			14
		OSCCAPx = 3h			18
C_XOUT	Integrated output capacitance⁽⁴⁾	OSCCAPx = 0h	3 V		0		pF
		OSCCAPx = 1h			10
		OSCCAPx = 2h			14
		OSCCAPx = 3h			18
V_IL	Input levels at XIN⁽³⁾		3 V	V_SS		0.2 × V_CC	V
V_IH	Input levels at XIN⁽³⁾		3 V	0.8 × V_CC		V_CC	V

(1) The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (C_XIN × C_XOUT) / (C_XIN + C_XOUT). This is independent of XTS_FLL.

(2) To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.

Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(3) Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.

(4) TI recommends external capacitance for precision real-time clock applications; OSCCAPx = 0h.

5.20 SD16 Power Supply and Operating Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP	MAX	UNIT
AV_CC	Analog supply voltage	AV_CC = DV_CC, AV_SS = DV_SS = 0 V			2.7		3.6	V
I_SD16	Analog supply current: 1 active SD16 channel including internal reference	SD16LP = 0, f_SD16 = 1 MHz, SD16OSR = 256	GAIN: 1, 2	3 V		650	950	µA
			GAIN: 4, 8, 16			730	1100
			GAIN: 32			1050	1550
		SD16LP = 1, f_SD16 = 0.5 MHz, SD16OSR = 256	GAIN: 1			620	930
		SD16LP = 1, f_SD16 = 0.5 MHz, SD16OSR = 256	GAIN: 32			700	1060
f_SD16	Analog front-end input clock frequency	SD16LP = 0 (low-power mode disabled)				1		MHz
f_SD16	Analog front-end input clock frequency	SD16LP = 1 (low-power mode enabled)				0.5		MHz

5.21 SD16 Analog Input Range⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_ID	Differential input voltage range for specified performance⁽²⁾	SD16GAINx = 1, SD16REFON = 1			±500		mV
		SD16GAINx = 2, SD16REFON = 1			±250
		SD16GAINx = 4, SD16REFON = 1			±125
		SD16GAINx = 8, SD16REFON = 1			±62
		SD16GAINx = 16, SD16REFON = 1			±31
		SD16GAINx = 32, SD16REFON = 1			±15
Z_I	Input impedance (one input pin to AV_SS)	f_SD16 = 1 MHz, SD16GAINx = 1	3 V		200		kΩ
Z_I	Input impedance (one input pin to AV_SS)	f_SD16 = 1 MHz, SD16GAINx = 32	3 V		75		kΩ
Z_ID	Differential input impedance (IN+ to IN−)	f_SD16 = 1 MHz, SD16GAINx = 1	3 V	300	400		kΩ
Z_ID	Differential input impedance (IN+ to IN−)	f_SD16 = 1 MHz, SD16GAINx = 32	3 V	100	150		kΩ
V_I	Absolute input voltage range			AV_SS – 1		AV_CC	V
V_IC	Common-mode input voltage range			AV_SS – 1		AV_CC	V

(1) All parameters pertain to each SD16 channel.

(2) The analog input range depends on the reference voltage applied to V_REF. If V_REF is sourced externally, the full-scale range is defined by V_FSR+ = +(V_REF / 2) / GAIN and V_FSR− = −(V_REF / 2) / GAIN. The analog input range should not exceed 80% of V_FSR+ or V_FSR−.

5.22 SD16 Analog Performance

f_SD16 = 1 MHz, SD16OSRx = 256, SD16REFON = 1, over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP	MAX	UNIT
SINAD	Signal-to-noise + distortion ratio	SD16GAINx = 1, signal amplitude = 500 mV	f_IN = 50 Hz or 100 Hz	3 V	83.5	85		dB
		SD16GAINx = 2, signal amplitude = 250 mV			81.5	84
		SD16GAINx = 4, signal amplitude = 125 mV			76	79.5
		SD16GAINx = 8, signal amplitude = 62 mV			73	76.5
		SD16GAINx = 16, signal amplitude = 31 mV			69	73
		SD16GAINx = 32, signal amplitude = 15 mV			62	69
G	Nominal gain	SD16GAINx = 1		3 V	0.97	1.00	1.02
		SD16GAINx = 2			1.90	1.96	2.02
		SD16GAINx = 4			3.76	3.86	3.96
		SD16GAINx = 8			7.36	7.62	7.84
		SD16GAINx = 16			14.56	15.04	15.52
		SD16GAINx = 32			27.20	28.35	29.76
E_OS	Offset error	SD16GAINx = 1		3 V			±0.2	%FSR
E_OS	Offset error	SD16GAINx = 32		3 V			±1.5	%FSR
dE_OS/dT	Offset error temperature coefficient	SD16GAINx = 1		3 V		±4	±20	ppm FSR/°C
dE_OS/dT	Offset error temperature coefficient	SD16GAINx = 32		3 V		±20	±100	ppm FSR/°C
CMRR	Common-mode rejection ratio	SD16GAINx = 1, Common-mode input signal: V_ID = 500 mV, f_IN = 50 Hz or 100 Hz		3 V		>90		dB
CMRR	Common-mode rejection ratio	SD16GAINx = 32, Common-mode input signal: V_ID = 16 mV, f_IN = 50 Hz or 100 Hz		3 V		>75		dB
AC PSRR	AC power-supply rejection ratio	SD16GAINx = 1, V_CC = 3 V ±100 mV, f_VCC = 50 Hz		3 V		>80		dB
XT	Crosstalk			3 V		<–100		dB

5.23 SD16 Built-in Temperature Sensor⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
TC_Sensor	Sensor temperature coefficient			1.18	1.32	1.46	mV/K
V_{Offset,sensor}	Sensor offset voltage			–100		100	mV
V_Sensor	Sensor output voltage⁽²⁾	Temperature sensor voltage at T_A = 85°C	3 V	435	475	515	mV
		Temperature sensor voltage at T_A = 25°C		355	395	435
		Temperature sensor voltage at T_A = 0°C		320	360	400

(1) The following formula can be used to calculate the temperature sensor output voltage:
V_Sensor,typ = TC_Sensor (273 + T [°C] ) + V_{Offset,sensor} [mV]

(2) Results based on characterization or production test, no TC_Sensor or V_{Offset,sensor}.

5.24 SD16 Built-in Voltage Reference

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_REF	Internal reference voltage	SD16REFON = 1, SD16VMIDON = 0	3 V	1.14	1.20	1.26	V
I_REF	Reference supply current	SD16REFON = 1, SD16VMIDON = 0	3 V		175	260	µA
TC	Temperature coefficient	SD16REFON = 1, SD16VMIDON = 0	3 V		20	50	ppm/K
C_REF	V_REF load capacitance	SD16REFON = 1 SD16VMIDON = 0⁽¹⁾			100		nF
I_LOAD	V_REF(I) maximum load current	SD16REFON = 0, SD16VMIDON = 0	3 V			±200	nA
t_ON	Turnon time	SD16REFON = 0 → 1, SD16VMIDON = 0, C_REF = 100 nF	3 V		5		ms
DC PSR	DC power supply rejection, ΔV_REF/ΔV_CC	SD16REFON = 1, SD16VMIDON = 0, V_CC = 2.5 V to 3.6 V			200		µV/V

(1) No capacitance is required on V_REF. However, TI recommends a capacitance of at least 100 nF to reduce any reference voltage noise.

5.25 SD16 Built-in Reference Output Buffer

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_REF,BUF	Reference buffer output voltage	SD16REFON = 1, SD16VMIDON = 1	3 V		1.2		V
I_REF,BUF	Reference supply and reference output buffer quiescent current	SD16REFON = 1, SD16VMIDON = 1	3 V		385	600	A
C_REF(O)	Required load capacitance on V_REF	SD16REFON = 1, SD16VMIDON = 1		470			nF
I_LOAD,Max	Maximum load current on V_REF	SD16REFON = 1, SD16VMIDON = 1	3 V			±1	mA
	Maximum voltage variation versus load current	\|I_LOAD\| = 0 to 1 mA	3 V	–15		+15	mV
t_ON	Turnon time	SD16REFON = 0 → 1, SD16VMIDON = 0, C_REF = 100 nF	3 V		100		µs

5.26 SD16 External Reference Input

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_REF(I)	Input voltage	SD16REFON = 0	3 V	1.0	1.25	1.5	V
I_REF(I)	Input current	SD16REFON = 0	3 V			50	nA

5.27 Flash Memory

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
V_{CC(PGM/ ERASE)}	Program and erase supply voltage			2.7		3.6	V
f_FTG	Flash timing generator frequency			257		476	kHz
I_PGM	Supply current from DV_CC during program		2.7 V, 3.6 V		3	5	mA
I_ERASE	Supply current from DV_CC during erase		2.7 V, 3.6 V		3	7	mA
t_CPT	Cumulative program time⁽¹⁾		2.7 V, 3.6 V			10	ms
t_CMErase	Cumulative mass erase time⁽²⁾		2.7 V, 3.6 V	200			ms
	Program and erase endurance			10⁴	10⁵		cycles
t_Retention	Data retention duration	T_J = 25°C		100			years
t_Word	Word or byte program time⁽³⁾				35		t_FTG
t_{Block, 0}	Block program time for first byte or word⁽³⁾				30
t_{Block, 1–63}	Block program time for each additional byte or word⁽³⁾				21
t_{Block, End}	Block program end-sequence wait time⁽³⁾				6
t_{Mass Erase}	Mass erase time⁽³⁾				5297
t_{Seg Erase}	Segment erase time⁽³⁾				4819

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word or byte write mode and block write mode.

(2) The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297 × (1 / f_FTG,max) = 5297 × (1 / 476 kHz)). To achieve the required cumulative mass erase time, the mass erase operation of the flash controller can be repeated until this time is met (a worst case minimum of 19 cycles is required).

(3) These values are hardwired into the state machine of the flash controller (t_FTG = 1 / f_FTG).

5.28 JTAG Interface

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
f_TCK	TCK input frequency	See ⁽¹⁾	2.2 V	0		5	MHz
f_TCK	TCK input frequency	See ⁽¹⁾	3V	0		10	MHz
R_Internal	Internal pullup resistance on TMS, TCK, TDI/TCLK	See ⁽²⁾	2.2 V, 3 V	25	60	90	kΩ

(1) f_TCK may be restricted to meet the timing requirements of the module selected.

(2) TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.

5.29 JTAG Fuse⁽¹⁾

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	MAX	UNIT
V_CC(FB)	Supply voltage during fuse-blow condition	T_A = 25°C	2.5		V
V_FB	Voltage level on TDI/TCLK for fuse-blow		6	7	V
I_FB	Supply current into TDI/TCLK during fuse blow			100	mA
t_FB	Time to blow fuse			1	ms

(1) After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to bypass mode.

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5 Specifications

5.1 Absolute Maximum Ratings(1)

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Supply Current Into AVCC and DVCC Excluding External Current(1)

5.5 Thermal Resistance Characteristics, PM Package (LQFP64)

5.6 Schmitt-Trigger Inputs − Ports (P1 and P2), RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)

5.7 Inputs P1.x, P2.x, TAx

5.8 Leakage Current − Ports (P1 and P2)(1)

5.9 Outputs − Ports (P1 and P2)

5.10 Output Frequency

5.11 Typical Characteristics – Ports P1 and P2

5.12 Wake-up Time From LPM3

5.13 RAM

5.14 LCD

5.15 USART0(1)

5.16 POR, BOR(1)

5.17 SVS (Supply Voltage Supervisor and Monitor)(3)

5.18 DCO

5.19 Crystal Oscillator, LFXT1 Oscillator(1) (2)

5.20 SD16 Power Supply and Operating Characteristics

5.21 SD16 Analog Input Range(1)

5.22 SD16 Analog Performance

5.23 SD16 Built-in Temperature Sensor(1)

5.24 SD16 Built-in Voltage Reference

5.25 SD16 Built-in Reference Output Buffer

5.26 SD16 External Reference Input

5.27 Flash Memory

5.28 JTAG Interface

5.29 JTAG Fuse(1)

5.1 Absolute Maximum Ratings⁽¹⁾

5.4 Supply Current Into AV_CC and DV_CC Excluding External Current⁽¹⁾

5.8 Leakage Current − Ports (P1 and P2)⁽¹⁾

5.15 USART0⁽¹⁾

5.16 POR, BOR⁽¹⁾

5.17 SVS (Supply Voltage Supervisor and Monitor)⁽³⁾

5.19 Crystal Oscillator, LFXT1 Oscillator⁽¹⁾ ⁽²⁾

5.21 SD16 Analog Input Range⁽¹⁾

5.23 SD16 Built-in Temperature Sensor⁽¹⁾

5.29 JTAG Fuse⁽¹⁾