ZHCS406R August   2010  – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.5, P3.2 to P3.7, and PJ.0 to PJ.6)
    8. 5.8  Schmitt-Trigger Inputs – General-Purpose I/O (P1.6 and P1.7, P2.0 to P2.7, and P3.0 and P3.1)
    9. 5.9  Inputs – Ports P1 and P2
    10. 5.10 Leakage Current – General-Purpose I/O
    11. 5.11 Outputs – Ports P1, P3, PJ (Full Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    12. 5.12 Outputs – Ports P1 to P3 (Full Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    13. 5.13 Outputs – Ports P1, P3, PJ (Reduced Drive Strength, P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6)
    14. 5.14 Outputs – Ports P1 to P3 (Reduced Drive Strength, P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1)
    15. 5.15 Output Frequency – Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    16. 5.16 Output Frequency – Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    17. 5.17 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    18. 5.18 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.0 to P1.5, P3.2 to P3.7, PJ.0 to PJ.6
    19. 5.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    20. 5.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1), Ports P1.6 and P1.7, P2.0 to P2.7, P3.0 and P3.1
    21. 5.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 5.22 Crystal Oscillator, XT1, High-Frequency Mode
    23. 5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 5.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 5.25 DCO Frequency
    26. 5.26 PMM, Brownout Reset (BOR)
    27. 5.27 PMM, Core Voltage
    28. 5.28 PMM, SVS High Side
    29. 5.29 PMM, SVM High Side
    30. 5.30 PMM, SVS Low Side
    31. 5.31 PMM, SVM Low Side
    32. 5.32 Wake-up Times From Low-Power Modes
    33. 5.33 Timer_A
    34. 5.34 USCI (UART Mode)
    35. 5.35 USCI (SPI Master Mode)
    36. 5.36 USCI (SPI Slave Mode)
    37. 5.37 USCI (I2C Mode)
    38. 5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)
    39. 5.39 10-Bit ADC, Timing Parameters (MSP430F51x2 Devices Only)
    40. 5.40 10-Bit ADC, Linearity Parameters (MSP430F51x2 Devices Only)
    41. 5.41 REF, External Reference (MSP430F51x2 Devices Only)
    42. 5.42 REF, Built-In Reference (MSP430F51x2 Devices Only)
    43. 5.43 Comparator_B
    44. 5.44 Timer_D, Power Supply and Reference Clock
    45. 5.45 Timer_D, Local Clock Generator Frequency
    46. 5.46 Timer_D, Trimmed Clock Frequencies
    47. 5.47 Timer_D, Frequency Multiplication Mode
    48. 5.48 Timer_D, Input Capture and Output Compare Timing
    49. 5.49 Flash Memory
    50. 5.50 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU
    2. 6.2  Instruction Set
    3. 6.3  Operating Modes
    4. 6.4  Interrupt Vector Addresses
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  Flash Memory
    8. 6.8  RAM
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O
      2. 6.9.2  Port Mapping Controller
      3. 6.9.3  Oscillator and System Clock
      4. 6.9.4  Power-Management Module (PMM)
      5. 6.9.5  Hardware Multiplier
      6. 6.9.6  Watchdog Timer (WDT_A)
      7. 6.9.7  System Module (SYS)
      8. 6.9.8  DMA Controller
      9. 6.9.9  Universal Serial Communication Interface (USCI)
      10. 6.9.10 TA0
      11. 6.9.11 TD0
      12. 6.9.12 TD1
      13. 6.9.13 Comparator_B
      14. 6.9.14 ADC10_A (MSP430F51x2 Only)
      15. 6.9.15 CRC16
      16. 6.9.16 Reference (REF) Module Voltage Reference
      17. 6.9.17 Embedded Emulation Module (EEM) (S Version)
      18. 6.9.18 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.5) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P1 (P1.6 to P1.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P3 (P3.0 and P3.1) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P3 (P3.2 and P3.3) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P3 (P3.4) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P3 (P3.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P3 (P3.6) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P3 (P3.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 6.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
      12. 6.10.12 Port J (PJ.4) Input/Output With Schmitt Trigger
      13. 6.10.13 Port J (PJ.5) Input/Output With Schmitt Trigger
      14. 6.10.14 Port J (PJ.6) Input/Output With Schmitt Trigger
    11. 6.11 Device Descriptors
  7. 7器件和文档支持
    1. 7.1  入门和后续步骤
    2. 7.2  Device Nomenclature
    3. 7.3  工具和软件
    4. 7.4  文档支持
    5. 7.5  相关链接
    6. 7.6  社区资源
    7. 7.7  商标
    8. 7.8  静电放电警告
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.38 10-Bit ADC, Power Supply and Input Range Conditions (MSP430F51x2 Devices Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
AVCC Analog supply voltage AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V		 1.8 3.6 V
V(Ax) Analog input voltage range(2) All ADC10_A pins: P1.0 to P1.5 and P3.6 and P3.7 terminals 0 AVCC V
IADC10_A Operating supply current into AVCC terminal, REF module and reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 00		 2.2 V 60 90 µA
3 V 75 100
Operating supply current into AVCC terminal, REF module on, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 1,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 01		 3 V 113 130
Operating supply current into AVCC terminal, REF module off, reference buffer on fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 10, VEREF = 2.5 V		 3 V 105 125
Operating supply current into AVCC terminal, REF module off, reference buffer off fADC10CLK = 5 MHz, ADC10ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC10DIV  = 0,
ADC10SREF = 11, VEREF = 2.5 V		 3 V 70 95
CI Input capacitance Only one terminal Ax can be selected at one time from the pad to the ADC10_A capacitor array including wiring and pad 2.2 V 3.5 pF
RI Input MUX ON resistance AVCC > 2.0 V, 0 V ≤ VAx ≤ AVCC 36 kΩ
1.8V < AVCC < 2.0 V, 0 V ≤ VAx ≤ AVCC 96
(1) The leakage current is defined in the leakage current table with P6.x/Ax parameter.
(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external reference voltage requires decoupling capacitors.
Two decoupling capacitors, 10 µF and 100 nF, should be connected to VEREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. Also see the MSP430x5xx and MSP430x6xx Family User's Guide.
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