ZHCS406R August 2010 – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| tTD,cap | Timer_D input capture timing, minimum pulse duration to trigger input capture event | fMAX = 262 MHz | 4 | ns | ||
| tTD0,cap,matching | Timer0_D input capture timing, matching between input capture channels P1.6 to P1.7 and P2.0 | fMAX = 262 MHz | 1 | 2 | LSB | |
| Timer0_D input capture timing, matching between input capture channels. P2.4 to P2.5 and P2.6 | fMAX = 262 MHz | 3 | 4 | |||
| tTD1,cap,matching | Timer1_D input capture timing, matching between input capture channels P2.1 to P2.2 and P2.3 | fMAX = 262 MHz | 2 | 3 | LSB | |
| Timer1_D input capture timing, matching between input capture channels. P2.7 to P3.0 and P3.1 | fMAX = 262 MHz | 2 | 4 | |||
| tTD01,cap,matching | Timer0_D and Timer1_D input capture timing, matching between input capture channels. Timer0_D is the high-resolution clock generator source. | fMAX = 262 MHz | 4 | 8 | LSB | |
| tTD0,comp,matching | Timer0_D output compare timing, matching between output capture compare channels for pins P1.6, P1.7, and P2.0 | Rising edges,
fMAX = 262 MHz |
4 | ns | ||
| Falling edges,
fMAX = 262 MHz |
4 | |||||
| Rising and falling edges,
fMAX = 262 MHz |
8 | |||||
| tTD1,comp,matching | Timer1_D output compare timing, matching between output capture compare channels for pins P2.1, P2.2, and P2.3 | Rising edges,
fMAX = 262 MHz |
4 | ns | ||
| Falling edges,
fMAX = 262 MHz |
4 | |||||
| Rising and falling edges,
fMAX = 262 MHz |
8 | |||||
| tTD01,comp,matching | Timer0_D and Timer1_D output compare timing, matching between output compare channels. Timer0_D is the high-resolution clock generator source | All edges,
fMAX = 262 MHz |
8 | LSB | ||