ZHCS406R August 2010 – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172
PRODUCTION DATA.
TD0 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz (4-ns) resolution. TD0 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TD0 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. External fault inputs as well as a external timer counter clear is supported along with interrupt flags from the TEC0 module.
| INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| RSB
(40-PIN QFN) |
DA
(38-PIN TSSOP) |
YFF
(40-PIN DSBGA) |
RSB
(40-PIN QFN) |
DA
(38-PIN TSSOP) |
YFF
(40-PIN DSBGA) |
|||||
| P3.4 - 31 | – | P3.4 - G5 | TD0CLK | TDCLK | Timer | NA | NA | – | – | – |
| ACLK (internal) | ACLK (internal) | ACLK (internal) | ACLK | ACLK | – | – | – | |||
| SMCLK (internal) | SMCLK (internal) | SMCLK (internal) | SMCLK | SMCLK | – | – | – | |||
| P3.4 - 31 | – | P3.4 - G5 | TD0CLK | TDCLK | – | – | – | |||
| – | – | – | – | CLK0 | – | – | – | |||
| P2.4 - 19 | P2.4 - 23 | P2.4 - B4 | TEC0CLR | TECXCLR | – | – | – | |||
| P1.6 - 11(1) | P1.6 - 15(1) | P1.6 - A1(1) | TD0.0 | CCI0A | CCR0 | TD0 | TD0 | P1.6 - 11(1) | P1.6 - 15(1) | P1.6 - A1(1) |
| P3.2 - 29 | P3.2 - 33 | P3.2 - F5 | TD0.0 | CCI0B | P2.4 - 19 | P2.4 - 23 | P2.4 - B4 | |||
| – | – | – | VSS | GND | ADC10_A (internal) ADC10SHSx = 010b (2) | ADC10_A (internal) ADC10SHSx = 010b(2) | ADC10_A (internal) ADC10SHSx = 010b(2) | |||
| – | – | – | VCC | VCC | – | – | – | |||
| P2.5 - 20 | P2.5 - 24 | P2.5 - A6 | TEC0FLT0 | TECXFLT0 | – | – | ||||
| P1.7 - 12(1) | P1.7 - 16(1) | P1.7 - B2(1) | TD0.1 | CCI1A | CCR1 | TD1 | TD1 | P1.7 - 12(1) | P1.7 - 16(1) | P1.7 - B2(1) |
| CBOUT (internal) | CBOUT (internal) | CBOUT (internal) | TD0.1 | CCI1B | PJ.6 - 28 | PJ.6 - 32 | PJ.6 - E5 | |||
| – | – | – | VSS | GND | P2.5 - 20 | P2.5 - 24 | P2.5 - A6 | |||
| – | – | – | VCC | VCC | ADC10_A (internal) ADC10SHSx = 011b (2) | ADC10_A (internal) ADC10SHSx = 011b (2) | ADC10_A (internal) ADC10SHSx = 011b (2) | |||
| P2.6 - 21 | P2.6 - 20 | P2.6 - B5 | TEC0FLT1 | TECXFLT1 | – | – | ||||
| P2.0 - 13(1) | P2.0 - 17(1) | P2.0 - B3(1) | TD0.2 | CCI2A | CCR2 | TD2 | TD2 | P2.0 - 13(1) | P2.0 - 17(1) | P2.0 - B3(1) |
| ACLK (internal) | ACLK (internal) | ACLK (internal) | TD0.2 | CCI2B | P2.6 - 21 | P2.6 - 25 | P2.6 - B5 | |||
| – | – | – | VSS | GND | – | – | – | |||
| – | – | – | VCC | VCC | – | – | – | |||
| P2.4 - 19 | P2.4 - 23 | P2.4 - B4 | TEC0FLT2 | TECXFLT2 | – | – | – | |||