ZHCS406R August 2010 – September 2018 MSP430F5131 , MSP430F5132 , MSP430F5151 , MSP430F5152 , MSP430F5171 , MSP430F5172
PRODUCTION DATA.
TD1 is a 16-bit timer/counter with three capture/compare registers supporting up to 256-MHz (4-ns) resolution. TD1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-12). TD1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. External fault inputs as well as a external timer counter clear is supported along with interrupt flags from the TEC0 module.
| INPUT PIN NUMBER | DEVICE INPUT SIGNAL | MODULE INPUT SIGNAL | MODULE BLOCK | MODULE OUTPUT SIGNAL | DEVICE OUTPUT SIGNAL | OUTPUT PIN NUMBER | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| RSB
(40-PIN QFN) |
DA
(38-PIN TSSOP) |
YFF
(40-PIN DSBGA) |
RSB
(40-PIN QFN) |
DA
(38-PIN TSSOP) |
YFF
(40-PIN DSBGA) |
|||||
| PJ.6 - 28 | PJ.6 - 32 | PJ.6 - E5 | TD1CLK | TDCLK | Timer | NA | NA | – | – | – |
| ACLK (internal) | ACLK (internal) | ACLK (internal) | ACLK | ACLK | – | – | – | |||
| SMCLK(internal) | SMCLK | SMCLK | SMCLK | SMCLK | – | – | – | |||
| PJ.6 - 28 | PJ.6 - 32 | PJ.6 - E5 | TD1CLK | TDCLK | – | – | – | |||
| – | – | – | from TD0 (internal) | CLK0 | ||||||
| P2.7 - 22 | P2.7 - 26 | P2.7 - C5 | TEC1CLR | TECxCLR | – | – | – | |||
| P2.1 - 14(1) | P2.1 - 18(1) | P2.1 - A2 | TD1.0 | CCI0A | CCR0 | TD0 | TD0 | P2.1 - 14(1) | P2.1 - 18(1) | P2.1 - A2(1) |
| – | – | – | TD1.0 | CCI0B | P2.7 - 22 | P2.7 - 26 | P2.7 - C5 | |||
| – | – | – | VSS | GND | – | – | – | |||
| – | – | – | VCC | VCC | – | – | – | |||
| P3.1 - 24 | P3.1 - 28 | P3.1 - C6 | TEC1FLT0 | TECXFLT0 | – | – | – | |||
| P2.2 - 15(1) | P2.2 - 19(1) | P2.2 - A3 | TD1.1 | CCI1A | CCR1 | TD1 | TD1 | P2.2 - 15(1) | P2.2 - 19(1) | P2.2 - A3(1) |
| CBOUT (internal) | CBOUT (internal) | CBOUT (internal) | TD1.1 | CCI1B | P3.0 - 23 | P3.0 - 27 | P3.0 - B6 | |||
| – | – | – | VSS | GND | – | – | – | |||
| – | – | – | VCC | VCC | – | – | – | |||
| P2.7 - 22 | P2.7 - 26 | P2.7 - C5 | TEC1FLT1 | TECXFLT1 | – | – | – | |||
| P2.3 - 16(1) | P2.3 - 20(1) | P2.3 - C4 | TD1.2 | CCI2A | CCR2 | TD2 | TD2 | P2.3 - 16(1) | P2.3 - 20(1) | P2.3 - C4(1) |
| ACLK (internal) | ACLK (internal) | ACLK (internal) | TD1.2 | CCI2B | P3.1 - 24 | P3.1 - 28 | P3.1 - C6 | |||
| – | – | – | VSS | GND | – | – | – | |||
| – | – | – | VCC | VCC | – | – | – | |||
| P3.0 - 23 | P3.0 - 27 | P3.0 - B6 | TEC1FLT2 | TECXFLT2 | – | – | – | |||