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ZHCSAJ5H November 2012 – September 2018 MSP430F5212 , MSP430F5214 , MSP430F5217 , MSP430F5219 , MSP430F5222 , MSP430F5224 , MSP430F5229

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

YFF|64
- MXBG124F
RGC|64
- MPQF125F
ZQE|80
- MPBG269E

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND102O

订购信息

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1 Terminal Functions

TERMINAL					I/O⁽¹⁾	SUPPLY	DESCRIPTION
NAME	NO.
NAME	RGC	ZQE	YFF	RGZ
P6.0/CB0/A0	1	A1	C2	46	I/O	DVCC	General-purpose digital I/O Comparator_B input CB0 Analog input A0 for ADC (not available on all device types)
P6.1/CB1/A1	2	B2	A1	47	I/O	DVCC	General-purpose digital I/O Comparator_B input CB1 Analog input A1 for ADC (not available on all device types)
P6.2/CB2/A2	3	B1	B2	48	I/O	DVCC	General-purpose digital I/O Comparator_B input CB2 Analog input A2 for ADC (not available on all device types)
P6.3/CB3/A3	4	C2	C3	1	I/O	DVCC	General-purpose digital I/O Comparator_B input CB3 Analog input A3 for ADC (not available on all device types)
P6.4/CB4/A4	5	C1	A2	2	I/O	DVCC	General-purpose digital I/O Comparator_B input CB4 Analog input A4 for ADC (not available on all device types)
P6.5/CB5/A5	6	D2	B3	3	I/O	DVCC	General-purpose digital I/O Comparator_B input CB5 Analog input A5 for ADC (not available on all device types)
P6.6/CB6/A6	7	D1	C4	N/A	I/O	DVCC	General-purpose digital I/O (not available on all device types) Comparator_B input CB6 (not available on all device types) Analog input A6 for ADC (not available on all device types)
P6.7/CB7/A7	8	D3	A3	N/A	I/O	DVCC	General-purpose digital I/O (not available on all device types) Comparator_B input CB7 (not available on all device types) Analog input A7 for ADC (not available on all device types)
P5.0/A8/VeREF+	9	E1	B4	4	I/O	DVCC	General-purpose digital I/O Analog input A8 for ADC (not available on all device types) Input for an external reference voltage to the ADC (not available on all device types)
P5.1/A9/VeREF-	10	E2	A4	5	I/O	DVCC	General-purpose digital I/O Analog input A9 for ADC (not available on all device types) Negative terminal for the ADC reference voltage for an external applied reference voltage (not available on all device types)
AVCC	11	F2	B5	6			Analog power supply
P5.4/XIN	12	F1	A5	7	I/O	DVCC	General-purpose digital I/O Input terminal for crystal oscillator XT1⁽⁶⁾
P5.5/XOUT	13	G1	A6	8	I/O	DVCC	General-purpose digital I/O Output terminal of crystal oscillator XT1
AVSS	14	G2	B6	9			Analog ground supply
DVCC	15	H1	A7	10			Digital power supply
DVSS	16	J1	A8	11			Digital ground supply
VCORE⁽³⁾	17	J2	B8	12		DVCC	Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK	18	H2	B7	13	I/O	DVCC	General-purpose digital I/O with port interrupt TA0 clock signal TA0CLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0	19	H3	C7	14	I/O	DVCC	General-purpose digital I/O with port interrupt TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output
P1.2/TA0.1	20	J3	C8	15	I/O	DVCC	General-purpose digital I/O with port interrupt TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input
P1.3/TA0.2	21	G4	C6	16	I/O	DVCC	General-purpose digital I/O with port interrupt TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3	22	H4	C5	17	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4	23	J4	D8	18	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT	24	G5	D7	19	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt TA1 clock signal TA1CLK input Comparator_B output
P1.7/TA1.0	25	H5	D6	20	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1	26	J5	E8	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA1 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.1/TA1.2	27	G6	D5	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA1 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.2/TA2CLK/SMCLK	28	J6	E7	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA2 clock signal TA2CLK input SMCLK output (not available on all device types)
P2.3/TA2.0	29	H6	F8	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P2.4/TA2.1	30	J7	E6	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P2.5/TA2.2	31	J8	F7	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) TA2 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P2.6/RTCCLK/DMAE0	32	J9	G8	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with port interrupt (not available on all device types) RTC clock output for calibration (not available on all device types) DMA external trigger input (not available on all device types)
P2.7/UCB0STE/ UCA0CLK	33	H7	F6	21	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Slave transmit enable – USCI_B0 SPI mode Clock signal input – USCI_A0 SPI slave mode Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/ UCB0SDA	34	H8	H8	22	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Slave in, master out – USCI_B0 SPI mode I²C data – USCI_B0 I²C mode
P3.1/UCB0SOMI/ UCB0SCL	35	H9	G7	23	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Slave out, master in – USCI_B0 SPI mode I²C clock – USCI_B0 I²C mode
P3.2/UCB0CLK/ UCA0STE	36	G8	G6	24	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Clock signal input – USCI_B0 SPI slave mode Clock signal output – USCI_B0 SPI master mode Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/ UCA0SIMO	37	G9	H7	25	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Transmit data – USCI_A0 UART mode Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/ UCA0SOMI	38	G7	G5	26	I/O	DVIO⁽⁴⁾	General-purpose digital I/O Receive data – USCI_A0 UART mode Slave out, master in – USCI_A0 SPI mode
DVSS	39	F9	H6	27			Digital ground supply
DVIO⁽⁵⁾	40	E9	H5	28			Digital I/O power supply
P4.0/PM_UCB1STE/ PM_UCA1CLK	41	E8	F5	29	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave transmit enable – USCI_B1 SPI mode Default mapping: Clock signal input – USCI_A1 SPI slave mode Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA	42	E7	H4	30	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave in, master out – USCI_B1 SPI mode Default mapping: I²C data – USCI_B1 I²C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL	43	D9	E5	31	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Slave out, master in – USCI_B1 SPI mode Default mapping: I²C clock – USCI_B1 I²C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE	44	D8	G4	32	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Clock signal input – USCI_B1 SPI slave mode Default mapping: Clock signal output – USCI_B1 SPI master mode Default mapping: Slave transmit enable – USCI_A1 SPI mode
P4.4/PM_UCA1TXD/ PM_UCA1SIMO	45	D7	H3	33	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Transmit data – USCI_A1 UART mode Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI	46	C9	F4	34	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Receive data – USCI_A1 UART mode Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE	47	C8	H2	35	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: no secondary function
P4.7/PM_NONE	48	C7	G3	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O with reconfigurable port mapping secondary function (not available on all device types) Default mapping: no secondary function (not available on all device types)
P7.0/TB0.0	49	B8, B9	H1	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on all device types)
P7.1/TB0.1	50	A9	G2	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on all device types)
P7.2/TB0.2	51	B7	F3	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on all device types)
P7.3/TB0.3	52	A8	G1	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on all device types)
P7.4/TB0.4	53	A7	F2	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on all device types)
P7.5/TB0.5	54	A6	F1	N/A	I/O	DVIO⁽⁴⁾	General-purpose digital I/O (not available on all device types) TB0 CCR5 capture: CCI5A input, compare: Out5 output (not available on all device types)
BSLEN	55	B6	E2	36	I	DVIO⁽⁴⁾	BSL enable with internal pulldown
RST/NMI	56	A5	E3	37	I	DVIO⁽⁴⁾	Reset input active low⁽¹⁰⁾⁽¹¹⁾ Nonmaskable interrupt input⁽¹⁰⁾
P5.2/XT2IN	57	B5	E1	38	I/O	DVCC	General-purpose digital I/O Input terminal for crystal oscillator XT2⁽⁷⁾
P5.3/XT2OUT	58	B4	D1	39	I/O	DVCC	General-purpose digital I/O Output terminal of crystal oscillator XT2
TEST/SBWTCK⁽⁸⁾	59	A4	E4	40	I	DVCC	Test mode pin – Selects four wire JTAG operation Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO⁽⁹⁾	60	C5	D2	41	I/O	DVCC	General-purpose digital I/O JTAG test data output port
PJ.1/TDI/TCLK⁽⁹⁾	61	C4	C1	42	I/O	DVCC	General-purpose digital I/O JTAG test data input or test clock input
PJ.2/TMS⁽⁹⁾	62	A3	D3	43	I/O	DVCC	General-purpose digital I/O JTAG test mode select
PJ.3/TCK⁽⁹⁾	63	B3	B1	44	I/O	DVCC	General-purpose digital I/O JTAG test clock
RSTDVCC/ SBWTDIO⁽⁹⁾	64	A2	D4	45	I/O	DVCC	Reset input, active-low⁽¹²⁾ Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
Reserved	N/A	⁽²⁾	N/A	N/A			Reserved
QFN Pad	Pad	N/A	N/A	Pad			QFN thermal pad. TI recommends connecting to V_SS.

(1) I = input, O = output, N/A = not available

(2) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.

(3) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, C_VCORE.

(4) This pin function is supplied by DVIO. See Section 5.8 for input and output requirements.

(5) The voltage on DVIO is not supervised or monitored.

(6) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.

(7) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.

(8) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions.

(9) See Section 6.6 for use with JTAG function.

(10) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, input swing levels from DVSS to DVIO are required.

(11) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(12) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI reset as found on other devices in the MSP430 family. See Section 6.5 and Section 6.6 for details regarding the use of this pin.