ZHCSIT2F September 2010 – September 2018 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310
PRODUCTION DATA.
- 1器件概述
- 2修订历史记录
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Active Mode Supply Current Into VCC Excluding External Current
- 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 5.6 Thermal Resistance Characteristics
- 5.7 Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
- 5.8 Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
- 5.9 Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
- 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
- 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 5.14 Crystal Oscillator, XT1, Low-Frequency Mode
- 5.15 Crystal Oscillator, XT2
- 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
- 5.18 DCO Frequency
- 5.19 PMM, Brownout Reset (BOR)
- 5.20 PMM, Core Voltage
- 5.21 PMM, SVS High Side
- 5.22 PMM, SVM High Side
- 5.23 PMM, SVS Low Side
- 5.24 PMM, SVM Low Side
- 5.25 Wake-up Times From Low-Power Modes and Reset
- 5.26 Timer_A
- 5.27 Timer_B
- 5.28 USCI (UART Mode) Clock Frequency
- 5.29 USCI (UART Mode)
- 5.30 USCI (SPI Master Mode) Clock Frequency
- 5.31 USCI (SPI Master Mode)
- 5.32 USCI (SPI Slave Mode)
- 5.33 USCI (I2C Mode)
- 5.34 10-Bit ADC, Power Supply and Input Range Conditions
- 5.35 10-Bit ADC, Timing Parameters
- 5.36 10-Bit ADC, Linearity Parameters
- 5.37 REF, External Reference
- 5.38 REF, Built-In Reference
- 5.39 Comparator_B
- 5.40 Ports PU.0 and PU.1
- 5.41 LDO-PWR (LDO Power System)
- 5.42 Flash Memory
- 5.43 JTAG and Spy-Bi-Wire Interface
-
6Detailed Description
- 6.1 CPU (Link to User's Guide)
- 6.2 Operating Modes
- 6.3 Interrupt Vector Addresses
- 6.4 Memory Organization
- 6.5 Bootloader (BSL)
- 6.6 JTAG Operation
- 6.7 Flash Memory (Link to User's Guide)
- 6.8 RAM (Link to User's Guide)
- 6.9
Peripherals
- 6.9.1 Digital I/O (Link to User's Guide)
- 6.9.2 Port Mapping Controller (Link to User's Guide)
- 6.9.3 Oscillator and System Clock (Link to User's Guide)
- 6.9.4 Power-Management Module (PMM) (Link to User's Guide)
- 6.9.5 Hardware Multiplier (Link to User's Guide)
- 6.9.6 Real-Time Clock (RTC_A) (Link to User's Guide)
- 6.9.7 Watchdog Timer (WDT_A) (Link to User's Guide)
- 6.9.8 System Module (SYS) (Link to User's Guide)
- 6.9.9 DMA Controller (Link to User's Guide)
- 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
- 6.9.11 TA0 (Link to User's Guide)
- 6.9.12 TA1 (Link to User's Guide)
- 6.9.13 TA2 (Link to User's Guide)
- 6.9.14 TB0 (Link to User's Guide)
- 6.9.15 Comparator_B (Link to User's Guide)
- 6.9.16 ADC10_A (Link to User's Guide)
- 6.9.17 CRC16 (Link to User's Guide)
- 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
- 6.9.19 LDO and Port U
- 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
- 6.10 Peripheral File Map
- 6.11
Input/Output Diagrams
- 6.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
- 6.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
- 6.11.3 Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
- 6.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 6.11.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
- 6.11.6 Port P5 (P5.2) Input/Output With Schmitt Trigger
- 6.11.7 Port P5 (P5.3) Input/Output With Schmitt Trigger
- 6.11.8 Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
- 6.11.9 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
- 6.11.10 Port U (PU.0 and PU.1) Input/Output
- 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 6.12 Device Descriptors
- 7器件和文档支持
- 8机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息
6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Figure 6-14 shows the port diagram. Table 6-52 summarizes the selection of the pin functions.
Figure 6-14 Port PJ (PJ.1 to PJ.3) Diagram Table 6-52 Port PJ (PJ.0 to PJ.3) Pin Functions
| PIN NAME (PJ.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) |
|---|---|---|---|
| PJDIR.x | |||
| PJ.0/TDO | 0 | PJ.0 (I/O)(2) | I: 0; O: 1 |
| TDO(3) | X | ||
| PJ.1/TDI/TCLK | 1 | PJ.1 (I/O)(2) | I: 0; O: 1 |
| TDI/TCLK(3)(4) | X | ||
| PJ.2/TMS | 2 | PJ.2 (I/O)(2) | I: 0; O: 1 |
| TMS(3)(4) | X | ||
| PJ.3/TCK | 3 | PJ.3 (I/O)(2) | I: 0; O: 1 |
| TCK(3)(4) | X |
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.