ZHCSIT2F September   2010  – September 2018 MSP430F5304 , MSP430F5308 , MSP430F5309 , MSP430F5310

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 5.15 Crystal Oscillator, XT2
    16. 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    17. 5.17 Internal Reference, Low-Frequency Oscillator (REFO)
    18. 5.18 DCO Frequency
    19. 5.19 PMM, Brownout Reset (BOR)
    20. 5.20 PMM, Core Voltage
    21. 5.21 PMM, SVS High Side
    22. 5.22 PMM, SVM High Side
    23. 5.23 PMM, SVS Low Side
    24. 5.24 PMM, SVM Low Side
    25. 5.25 Wake-up Times From Low-Power Modes and Reset
    26. 5.26 Timer_A
    27. 5.27 Timer_B
    28. 5.28 USCI (UART Mode) Clock Frequency
    29. 5.29 USCI (UART Mode)
    30. 5.30 USCI (SPI Master Mode) Clock Frequency
    31. 5.31 USCI (SPI Master Mode)
    32. 5.32 USCI (SPI Slave Mode)
    33. 5.33 USCI (I2C Mode)
    34. 5.34 10-Bit ADC, Power Supply and Input Range Conditions
    35. 5.35 10-Bit ADC, Timing Parameters
    36. 5.36 10-Bit ADC, Linearity Parameters
    37. 5.37 REF, External Reference
    38. 5.38 REF, Built-In Reference
    39. 5.39 Comparator_B
    40. 5.40 Ports PU.0 and PU.1
    41. 5.41 LDO-PWR (LDO Power System)
    42. 5.42 Flash Memory
    43. 5.43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC10_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Reference (REF) Module Voltage Reference (Link to User's Guide)
      19. 6.9.19 LDO and Port U
      20. 6.9.20 Embedded Emulation Module (EEM) (S Version) (Link to User's Guide)
    10. 6.10 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.11.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P5 (P5.2) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P5 (P5.3) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.11.10 Port U (PU.0 and PU.1) Input/Output
      11. 6.11.11 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      12. 6.11.12 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    12. 6.12 Device Descriptors
  7. 7器件和文档支持
    1. 7.1 入门和后续步骤
    2. 7.2 Device Nomenclature
    3. 7.3 工具与软件
    4. 7.4 文档支持
    5. 7.5 相关链接
    6. 7.6 社区资源
    7. 7.7 商标
    8. 7.8 静电放电警告
    9. 7.9 Glossary
  8. 8机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.43 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 2.2 V, 3 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 2.2 V, 3 V 0.025 15 µs
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 2.2 V, 3 V 1 µs
tSBW,Rst Spy-Bi-Wire return to normal operation time 15 100 µs
fTCK TCK input frequency, 4-wire JTAG(2) 2.2 V 0 5 MHz
3 V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 2.2 V, 3 V 45 60 80 kΩ
(1) Tools that access the Spy-Bi-Wire and BSL interfaces must wait for the tSBW,En time after the first transition of the TEST/SBWTCK pin (low to high), before the second transition of the pin (high to low) during the entry sequence.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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