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ZHCSIR8F August 2009 – September 2018 MSP430F5418 , MSP430F5419 , MSP430F5435 , MSP430F5436 , MSP430F5437 , MSP430F5438

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽¹⁾⁽²⁾

DEVICE	FLASH (KB)	SRAM (KB)	Timer_A⁽³⁾	Timer_B⁽⁴⁾	USCI		ADC12_A (Ch)	I/Os	PACKAGE
DEVICE	FLASH (KB)	SRAM (KB)	Timer_A⁽³⁾	Timer_B⁽⁴⁾	CHANNEL A: UART, IrDA, SPI	CHANNEL B: SPI, I²C	ADC12_A (Ch)	I/Os	PACKAGE
MSP430F5438	256	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ
MSP430F5437	256	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN
MSP430F5436	192	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ
MSP430F5435	192	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN
MSP430F5419	128	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ
MSP430F5418	128	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN

(1) For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.