ZHCS888H January 2010 – May 2021 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A
PRODUCTION DATA
- 1 特性
- 2 应用范围
- 3 说明
- 4 功能方框图
- 5 Revision History
- 6 Device Comparison
- 7 Terminal Configuration and Functions
-
8 Specifications
- 8.1 Absolute Maximum Ratings
- 8.2 ESD Ratings
- 8.3 Recommended Operating Conditions
- 8.4 Active Mode Supply Current Into VCC Excluding External Current
- 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 8.6 Thermal Resistance Characteristics
- 8.7 Schmitt-Trigger Inputs – General-Purpose I/O
- 8.8 Inputs – Ports P1 and P2
- 8.9 Leakage Current – General-Purpose I/O
- 8.10 Outputs – General-Purpose I/O (Full Drive Strength)
- 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
- 8.12 Output Frequency – General-Purpose I/O
- 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
- 8.16 Crystal Oscillator, XT1, High-Frequency Mode
- 8.17 Crystal Oscillator, XT2
- 8.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 8.19 Internal Reference, Low-Frequency Oscillator (REFO)
- 8.20 DCO Frequency
- 8.21 PMM, Brownout Reset (BOR)
- 8.22 PMM, Core Voltage
- 8.23 PMM, SVS High Side
- 8.24 PMM, SVM High Side
- 8.25 PMM, SVS Low Side
- 8.26 PMM, SVM Low Side
- 8.27 Wake-up Times From Low-Power Modes and Reset
- 8.28 Timer_A
- 8.29 Timer_B
- 8.30 USCI (UART Mode) Clock Frequency
- 8.31 USCI (UART Mode)
- 8.32 USCI (SPI Master Mode) Clock Frequency
- 8.33 USCI (SPI Master Mode)
- 8.34 USCI (SPI Slave Mode)
- 8.35 USCI (I2C Mode)
- 8.36 12-Bit ADC, Power Supply and Input Range Conditions
- 8.37 12-Bit ADC, Timing Parameters
- 8.38 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
- 8.39 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
- 8.40 12-Bit ADC, Temperature Sensor and Built-In VMID
- 8.41 REF, External Reference
- 8.42 REF, Built-In Reference
- 8.43 Flash Memory
- 8.44 JTAG and Spy-Bi-Wire Interface
-
9 Detailed Description
- 9.1 CPU
- 9.2 Operating Modes
- 9.3 Interrupt Vector Addresses
- 9.4 Memory Organization
- 9.5 Bootloader (BSL)
- 9.6 JTAG Operation
- 9.7 Flash Memory
- 9.8 RAM
- 9.9
Peripherals
- 9.9.1 Digital I/O
- 9.9.2 Oscillator and System Clock
- 9.9.3 Power-Management Module (PMM)
- 9.9.4 Hardware Multiplier (MPY)
- 9.9.5 Real-Time Clock (RTC_A)
- 9.9.6 Watchdog Timer (WDT_A)
- 9.9.7 System Module (SYS)
- 9.9.8 DMA Controller
- 9.9.9 Universal Serial Communication Interface (USCI)
- 9.9.10 TA0
- 9.9.11 TA1
- 9.9.12 TB0
- 9.9.13 ADC12_A
- 9.9.14 CRC16
- 9.9.15 Reference (REF) Module Voltage Reference
- 9.9.16 Embedded Emulation Module (EEM) (L Version)
- 9.9.17 Peripheral File Map
- 9.10
Input/Output Diagrams
- 9.10.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
- 9.10.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
- 9.10.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
- 9.10.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
- 9.10.5 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
- 9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
- 9.10.7 Port P5 (P5.4 to P5.7) Input/Output With Schmitt Trigger
- 9.10.8 Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
- 9.10.9 Port P7 (P7.0 and P7.1) Input/Output With Schmitt Trigger
- 9.10.10 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
- 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
- 9.10.12 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
- 9.10.13 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
- 9.10.14 Port P10 (P10.0 to P10.7) Input/Output With Schmitt Trigger
- 9.10.15 Port P11 (P11.0 to P11.2) Input/Output With Schmitt Trigger
- 9.10.16 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 9.10.17 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 9.11 Device Descriptors
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- PZ|100
订购信息
9.10.6 Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
Figure 9-7 and Figure 9-8 show the port diagrams. Table 9-48 summarizes the selection of the pin functions.
Figure 9-7 Port P5 (P5.2) Diagram
Figure 9-8 Port P5 (P5.3) DiagramTable 9-48 Port P5 (P5.2 and P5.3) Pin Functions
| PIN NAME (P5.x) | x | FUNCTION | CONTROL BITS OR SIGNALS(1) | |||
|---|---|---|---|---|---|---|
| P5DIR.x | P5SEL.2 | P5SEL.3 | XT2BYPASS | |||
| P5.2/XT2IN | 2 | P5.2 (I/O) | I: 0; O: 1 | 0 | X | X |
| XT2IN crystal mode(2) | X | 1 | X | 0 | ||
| XT2IN bypass mode(2) | X | 1 | X | 1 | ||
| P5.3/XT2OUT | 3 | P5.3 (I/O) | I: 0; O: 1 | 0 | 0 | X |
| XT2OUT crystal mode(3) | X | 1 | X | 0 | ||
| P5.3 (I/O)(3) | X | 1 | 0 | 1 | ||
(1) X = Don't care
(2) Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal mode or bypass mode.
(3) Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as general-purpose I/O.