6 Device Comparison

Table 6-1 summarizes the available family members.

Table 6-1 Device Characteristics

DEVICE⁽¹⁾	FLASH (KB)⁽²⁾	SRAM (KB)	Timer_A⁽³⁾	Timer_B⁽⁴⁾	USCI		ADC12_A (Ch)	I/O	PACKAGE
DEVICE⁽¹⁾	FLASH (KB)⁽²⁾	SRAM (KB)	Timer_A⁽³⁾	Timer_B⁽⁴⁾	CHANNEL A: UART, IrDA, SPI	CHANNEL B: SPI, I²C	ADC12_A (Ch)	I/O	PACKAGE
MSP430F5438A	256	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ, 113 ZCA, 113 ZQW
MSP430F5437A	256	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN
MSP430F5436A	192	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ, 113 ZCA, 113 ZQW
MSP430F5435A	192	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN
MSP430F5419A	128	16	5, 3	7	4	4	14 ext, 2 int	87	100 PZ, 113 ZCA, 113 ZQW
MSP430F5418A	128	16	5, 3	7	2	2	14 ext, 2 int	67	80 PN

(1) For the most current part, package, and ordering information, see the Package Option Addendum in Section 11, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators.