米6体育平台手机版

ZHCS888H January 2010 – May 2021 MSP430F5418A , MSP430F5419A , MSP430F5435A , MSP430F5436A , MSP430F5437A , MSP430F5438A

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ZCA|113
- MPBGAJ3A
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

9.3 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-1 Interrupt Sources, Flags, and Vectors

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power up External reset Watchdog time-out, password violation Flash memory password violation PMM password violation	WDTIFG, KEYV (SYSRSTIV)⁽¹⁾ ⁽³⁾	Reset	0FFFEh	63, highest
System NMI PMM Vacant memory access JTAG mailbox	SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)⁽¹⁾	(Non)maskable	0FFFCh	62
User NMI NMI Oscillator fault Flash memory access violation	NMIIFG, OFIFG, ACCVIFG (SYSUNIV)⁽¹⁾ ⁽³⁾	(Non)maskable	0FFFAh	61
TB0	TBCCR0 CCIFG0 ⁽²⁾	Maskable	0FFF8h	60
TB0	TBCCR1 CCIFG1 to TBCCR6 CCIFG6, TBIFG (TBIV)⁽¹⁾⁽²⁾	Maskable	0FFF6h	59
Watchdog timer interval timer mode	WDTIFG	Maskable	0FFF4h	58
USCI_A0 receive and transmit	UCA0RXIFG, UCA0TXIFG (UCA0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFF2h	57
USCI_B0 receive and transmit	UCB0RXIFG, UCB0TXIFG (UCB0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFF0h	56
ADC12_A	ADC12IFG0 to ADC12IFG15 (ADC12IV)⁽¹⁾ ⁽²⁾	Maskable	0FFEEh	55
TA0	TA0CCR0 CCIFG0⁽²⁾	Maskable	0FFECh	54
TA0	TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV)⁽¹⁾ ⁽²⁾	Maskable	0FFEAh	53
USCI_A2 receive and transmit	UCA2RXIFG, UCA2TXIFG (UCA2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFE8h	52
USCI_B2 receive and transmit	UCB2RXIFG, UCB2TXIFG (UCB2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFE6h	51
DMA	DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)⁽¹⁾ ⁽²⁾	Maskable	0FFE4h	50
TA1	TA1CCR0 CCIFG0⁽²⁾	Maskable	0FFE2h	49
TA1	TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFE0h	48
I/O Port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDEh	47
USCI_A1 receive and transmit	UCA1RXIFG, UCA1TXIFG (UCA1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDCh	46
USCI_B1 receive and transmit	UCB1RXIFG, UCB1TXIFG (UCB1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDAh	45
USCI_A3 receive and transmit	UCA3RXIFG, UCA3TXIFG (UCA3IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD8h	44
USCI_B3 receive and transmit	UCB3RXIFG, UCB3TXIFG (UCB3IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD6h	43
I/O Port P2	P2IFG.0 to P2IFG.7 (P2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD4h	42
RTC_A	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)⁽¹⁾ ⁽²⁾	Maskable	0FFD2h	41
Reserved	Reserved⁽⁴⁾		0FFD0h	40
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) Interrupt flags are in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.