米6体育平台手机版

ZHCS897K July 2009 – September 2018 MSP430F5500 , MSP430F5501 , MSP430F5502 , MSP430F5503 , MSP430F5504 , MSP430F5505 , MSP430F5506 , MSP430F5507 , MSP430F5508 , MSP430F5509 , MSP430F5510

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND031W

订购信息

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison⁽¹⁾⁽²⁾

DEVICE	PROGRAM MEMORY (KB)	SRAM (KB)⁽⁵⁾	Timer_A⁽³⁾	Timer_B⁽⁴⁾	USCI		ADC10_A (CH)	Comp_B (CH)	I/Os	PACKAGE
DEVICE	PROGRAM MEMORY (KB)	SRAM (KB)⁽⁵⁾	Timer_A⁽³⁾	Timer_B⁽⁴⁾	CHANNEL A: UART, LIN, IrDA, SPI	CHANNEL B: SPI, I²C	ADC10_A (CH)	Comp_B (CH)	I/Os	PACKAGE
MSP430F5510	32	4 + 2	5, 3, 3	7	2	2	10 ext, 2 int	8	47	64 RGC, 80 ZQE
MSP430F5510	32	4 + 2	5, 3, 3	7	2⁽⁶⁾	2⁽⁶⁾	6 ext, 2 int	4	31	48 PT, 48 RGZ
MSP430F5509	24	4 + 2	5, 3, 3	7	2	2	10 ext, 2 int	8	47	64 RGC, 80 ZQE
MSP430F5509	24	4 + 2	5, 3, 3	7	2⁽⁶⁾	2⁽⁶⁾	6 ext, 2 int	4	31	48 PT, 48 RGZ,
MSP430F5508	16	4 + 2	5, 3, 3	7	2	2	10 ext, 2 int	8	47	64 RGC, 80 ZQE
MSP430F5508	16	4 + 2	5, 3, 3	7	2⁽⁶⁾	2⁽⁶⁾	6 ext, 2 int	4	31	48 PT, 48 RGZ,
MSP430F5507	32	4 + 2	5, 3, 3	7	1	1	6 ext, 2 int	–	31	48 RGZ
MSP430F5506	24	4 + 2	5, 3, 3	7	1	1	6 ext, 2 int	–	31	48 RGZ
MSP430F5505	16	4 + 2	5, 3, 3	7	1	1	6 ext, 2 int	–	31	48 RGZ
MSP430F5504	8	4 + 2	5, 3, 3	7	1	1	6 ext, 2 int	–	31	48 PT, 48 RGZ
MSP430F5503	32	4 + 2	5, 3, 3	7	1	1	–	4	31	48 RGZ
MSP430F5502	24	4 + 2	5, 3, 3	7	1	1	–	4	31	48 RGZ
MSP430F5501	16	4 + 2	5, 3, 3	7	1	1	–	4	31	48 RGZ
MSP430F5500	8	4 + 2	5, 3, 3	7	1	1	–	4	31	48 RGZ

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.

(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.

(5) The additional 2KB USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.

(6) Two USCIs are available; however, pinned out functions are limited to what the user configures on port 4 with the port mapping controller (see Section 6.9.2). It may not be possible to bring out all functions simultaneously.