米6体育平台手机版

ZHCS409G June 2010 – September 2020 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ZQW|113
- MPBG674
ZCA|113
- MPBGAJ3A
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

8.48 12-Bit DAC, Reference Input Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
VeREF+	Reference input voltage range	DAC12IR = 0⁽¹⁾ ⁽²⁾	2.2 V, 3 V		AV_CC / 3	AV_CC + 0.2	V
VeREF+	Reference input voltage range	DAC12IR = 1⁽³⁾ ⁽⁴⁾	2.2 V, 3 V		AV_CC	AV_CC + 0.2	V
Ri_(VREF+), Ri_(VeREF+)	Reference input resistance	DAC12_0 IR = DAC12_1 IR = 0	2.2 V, 3 V	20			MΩ
		DAC12_0 IR = 1, DAC12_1 IR = 0			48		kΩ
		DAC12_0 IR = 0, DAC12_1 IR = 1			48
		DAC12_0 IR = DAC12_1 IR = 1, DAC12_0 SREFx = DAC12_1 SREFx⁽⁵⁾			24

(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

(2) The maximum voltage applied at reference input voltage terminal VeREF+ = (AV_CC – V_E(O)) / (3 × (1 + E_G)).

(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).

(4) The maximum voltage applied at reference input voltage terminal VeREF+ = (AV_CC – V_E(O)) / (1 + E_G).

(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel reducing the reference input resistance.