米6体育平台手机版

ZHCS409G June 2010 – September 2020 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ZQW|113
- MPBG674
ZCA|113
- MPBGAJ3A
PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

订购信息

9.5 Interrupt Vector Addresses

The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table 9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

Table 9-3 Interrupt Sources, Flags, and Vectors of MSP430F663x Configurations

INTERRUPT SOURCE	INTERRUPT FLAG	SYSTEM INTERRUPT	WORD ADDRESS	PRIORITY
System Reset Power-Up, External Reset Watchdog Time-out, Key Violation Flash Memory Key Violation	WDTIFG, KEYV (SYSRSTIV)⁽¹⁾⁽³⁾	Reset	0FFFEh	63, highest
System NMI PMM Vacant Memory Access JTAG Mailbox	SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, JMBOUTIFG (SYSSNIV)⁽¹⁾	(Non)maskable	0FFFCh	62
User NMI NMI Oscillator Fault Flash Memory Access Violation	NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)⁽¹⁾⁽³⁾	(Non)maskable	0FFFAh	61
Comp_B	Comparator B interrupt flags (CBIV)⁽¹⁾⁽²⁾	Maskable	0FFF8h	60
Timer TB0	TB0CCR0 CCIFG0⁽²⁾	Maskable	0FFF6h	59
Timer TB0	TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0IFG (TBIV)⁽¹⁾ ⁽²⁾	Maskable	0FFF4h	58
Watchdog Interval Timer Mode	WDTIFG	Maskable	0FFF2h	57
USCI_A0 Receive or Transmit	UCA0RXIFG, UCA0TXIFG (UCA0IV)⁽¹⁾⁽²⁾	Maskable	0FFF0h	56
USCI_B0 Receive or Transmit	UCB0RXIFG, UCB0TXIFG (UCB0IV)⁽¹⁾⁽²⁾	Maskable	0FFEEh	55
ADC12_A⁽⁵⁾	ADC12IFG0 to ADC12IFG15 (ADC12IV)⁽¹⁾⁽²⁾	Maskable	0FFECh	54
Timer TA0	TA0CCR0 CCIFG0⁽²⁾	Maskable	0FFEAh	53
Timer TA0	TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0IFG (TA0IV)⁽¹⁾⁽²⁾	Maskable	0FFE8h	52
USB_UBM	USB interrupts (USBIV)⁽¹⁾⁽²⁾	Maskable	0FFE6h	51
DMA	DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG, DMA4IFG, DMA5IFG (DMAIV)⁽¹⁾⁽²⁾	Maskable	0FFE4h	50
Timer TA1	TA1CCR0 CCIFG0⁽²⁾	Maskable	0FFE2h	49
Timer TA1	TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1IFG (TA1IV)⁽¹⁾⁽²⁾	Maskable	0FFE0h	48
I/O Port P1	P1IFG.0 to P1IFG.7 (P1IV)⁽¹⁾ ⁽²⁾	Maskable	0FFDEh	47
USCI_A1 Receive or Transmit	UCA1RXIFG, UCA1TXIFG (UCA1IV)⁽¹⁾⁽²⁾	Maskable	0FFDCh	46
USCI_B1 Receive or Transmit	UCB1RXIFG, UCB1TXIFG (UCB1IV)⁽¹⁾⁽²⁾	Maskable	0FFDAh	45
I/O Port P2	P2IFG.0 to P2IFG.7 (P2IV)⁽¹⁾ ⁽²⁾	Maskable	0FFD8h	44
LCD_B	LCD_B Interrupt Flags (LCDBIV)⁽¹⁾	Maskable	0FFD6h	43
RTC_B	RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)⁽¹⁾⁽²⁾	Maskable	0FFD4h	42
DAC12_A⁽⁶⁾	DAC12_0IFG, DAC12_1IFG⁽¹⁾⁽²⁾	Maskable	0FFD2h	41
Timer TA2	TA2CCR0 CCIFG0⁽²⁾	Maskable	0FFD0h	40
Timer TA2	TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2IFG (TA2IV)⁽¹⁾⁽²⁾	Maskable	0FFCEh	39
I/O Port P3	P3IFG.0 to P3IFG.7 (P3IV)⁽¹⁾⁽²⁾	Maskable	0FFCCh	38
I/O Port P4	P4IFG.0 to P4IFG.7 (P4IV)⁽¹⁾⁽²⁾	Maskable	0FFCAh	37
Reserved	Reserved⁽⁴⁾		0FFC8h	36
			⋮	⋮
			0FF80h	0, lowest

(1) Multiple source flags

(2) Interrupt flags are in the module.

(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, TI recommends reserving these locations.

(5) Only on devices with peripheral module ADC12_A, otherwise reserved.

(6) Only on devices with peripheral module DAC12_A, otherwise reserved.