ZHCS409G June 2010 – September 2020 MSP430F6630 , MSP430F6631 , MSP430F6632 , MSP430F6633 , MSP430F6634 , MSP430F6635 , MSP430F6636 , MSP430F6637 , MSP430F6638
PRODUCTION DATA
Table 7-1 describes the signals for all device variants and packages.
| TERMINAL | I/O(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO.(4) | |||
| PZ | ZCA, ZQW | |||
| P6.4/CB4/A4 | 1 | A1 | I/O | General-purpose digital I/O
Comparator_B input CB4 Analog input A4 – ADC (not available on F6632, F6631, and F6630 devices) |
| P6.5/CB5/A5 | 2 | B2 | I/O | General-purpose digital I/O
Comparator_B input CB5 Analog input A5 – ADC (not available on F6632, F6631, and F6630 devices) |
| P6.6/CB6/A6/DAC0 | 3 | B1 | I/O | General-purpose digital I/O
Comparator_B input CB6 Analog input A6 – ADC (not available on F6632, F6631, and F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, and F6630 devices) |
| P6.7/CB7/A7/DAC1 | 4 | C2 | I/O | General-purpose digital I/O
Comparator_B input CB7 Analog input A7 – ADC (not available on F6632, F6631, and F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, and F6630 devices) |
| P7.4/CB8/A12 | 5 | C1 | I/O | General-purpose digital I/O
Comparator_B input CB8 Analog input A12 –ADC (not available on F6632, F6631, and F6630 devices) |
| P7.5/CB9/A13 | 6 | C3 | I/O | General-purpose digital I/O
Comparator_B input CB9 Analog input A13 – ADC (not available on F6632, F6631, and F6630 devices) |
| P7.6/CB10/A14/DAC0 | 7 | D2 | I/O | General-purpose digital I/O
Comparator_B input CB10 Analog input A14 – ADC (not available on F6632, F6631, and F6630 devices) DAC12.0 output (not available on F6635, F6634, F6633, F6632, F6631, and F6630 devices) |
| P7.7/CB11/A15/DAC1 | 8 | D1 | I/O | General-purpose digital I/O
Comparator_B input CB11 Analog input A15 – ADC (not available on F6632, F6631, and F6630 devices) DAC12.1 output (not available on F6635, F6634, F6633, F6632, F6631, and F6630 devices) |
| P5.0/VREF+/VeREF+ | 9 | D4 | I/O | General-purpose digital I/O
Output of reference voltage to the ADC Input for an external reference voltage to the ADC |
| P5.1/VREF-/VeREF- | 10 | E4 | I/O | General-purpose digital I/O
Negative terminal for the reference voltage of the ADC for both sources, the internal reference voltage, or an external applied reference voltage |
| AVCC1 | 11 | E1, E2 | Analog power supply | |
| AVSS1 | 12 | F2 | Analog ground supply | |
| XIN | 13 | F1 | I | Input terminal for crystal oscillator XT1 |
| XOUT | 14 | G1 | O | Output terminal of crystal oscillator XT1 |
| AVSS2 | 15 | G2 | Analog ground supply | |
| P5.6/ADC12CLK/DMAE0 | 16 | H1 | I/O | General-purpose digital I/O
Conversion clock output ADC (not available on F6632, F6631, and F6630 devices) DMA external trigger input |
| P2.0/P2MAP0 | 17 | G4 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output |
| P2.1/P2MAP1 | 18 | H2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data |
| P2.2/P2MAP2 | 19 | J1 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock |
| P2.3/P2MAP3 | 20 | H4 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable |
| P2.4/P2MAP4 | 21 | J2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out |
| P2.5/P2MAP5 | 22 | K1 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in |
| P2.6/P2MAP6/R03 | 23 | K2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function Input/output port of lowest analog LCD voltage (V5) |
| P2.7/P2MAP7/LCDREF/R13 | 24 | L2 | I/O | General-purpose digital I/O with port interrupt and mappable secondary function
Default mapping: no secondary function External reference voltage input for regulated LCD voltage Input/output port of third most positive analog LCD voltage (V3 or V4) |
| DVCC1 | 25 | L1 | Digital power supply | |
| DVSS1 | 26 | M1 | Digital ground supply | |
| VCORE(2) | 27 | M2 | Regulated core power supply (internal use only, no external current loading) | |
| P5.2/R23 | 28 | L3 | I/O | General-purpose digital I/O
Input/output port of second most positive analog LCD voltage (V2) |
| LCDCAP/R33 | 29 | M3 | I/O | LCD capacitor connection
Input/output port of most positive analog LCD voltage (V1) CAUTION: CAUTION: LCDCAP/R33 must be connected to DVSS if not used. |
| COM0 | 30 | J4 | O | LCD common output COM0 for LCD backplane |
| P5.3/COM1/S42 | 31 | L4 | I/O | General-purpose digital I/O
LCD common output COM1 for LCD backplane LCD segment output S42 |
| P5.4/COM2/S41 | 32 | M4 | I/O | General-purpose digital I/O
LCD common output COM2 for LCD backplane LCD segment output S41 |
| P5.5/COM3/S40 | 33 | J5 | I/O | General-purpose digital I/O
LCD common output COM3 for LCD backplane LCD segment output S40 |
| P1.0/TA0CLK/ACLK/S39 | 34 | L5 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 clock signal TACLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) LCD segment output S39 |
| P1.1/TA0.0/S38 | 35 | M5 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output LCD segment output S38 |
| P1.2/TA0.1/S37 | 36 | J6 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input LCD segment output S37 |
| P1.3/TA0.2/S36 | 37 | H6 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output LCD segment output S36 |
| P1.4/TA0.3/S35 | 38 | M6 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output LCD segment output S35 |
| P1.5/TA0.4/S34 | 39 | L6 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output LCD segment output S34 |
| P1.6/TA0.1/S33 | 40 | J7 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output LCD segment output S33 |
| P1.7/TA0.2/S32 | 41 | M7 | I/O | General-purpose digital I/O with port interrupt
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output LCD segment output S32 |
| P3.0/TA1CLK/CBOUT/S31 | 42 | L7 | I/O | General-purpose digital I/O with port interrupt
Timer TA1 clock input Comparator_B output LCD segment output S31 |
| P3.1/TA1.0/S30 | 43 | H7 | I/O | General-purpose digital I/O with port interrupt
Timer TA1 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S30 |
| P3.2/TA1.1/S29 | 44 | M8 | I/O | General-purpose digital I/O with port interrupt
Timer TA1 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S29 |
| P3.3/TA1.2/S28 | 45 | L8 | I/O | General-purpose digital I/O with port interrupt
Timer TA1 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S28 |
| P3.4/TA2CLK/SMCLK/S27 | 46 | J8 | I/O | General-purpose digital I/O with port interrupt
Timer TA2 clock input SMCLK output LCD segment output S27 |
| P3.5/TA2.0/S26 | 47 | M9 | I/O | General-purpose digital I/O with port interrupt
Timer TA2 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S26 |
| P3.6/TA2.1/S25 | 48 | L9 | I/O | General-purpose digital I/O with port interrupt
Timer TA2 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S25 |
| P3.7/TA2.2/S24 | 49 | M10 | I/O | General-purpose digital I/O with port interrupt
Timer TA2 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S24 |
| P4.0/TB0.0/S23 | 50 | J9 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR0: CCI0A/CCI0B input, compare: Out0 output LCD segment output S23 |
| P4.1/TB0.1/S22 | 51 | M11 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR1: CCI1A/CCI1B input, compare: Out1 output LCD segment output S22 |
| P4.2/TB0.2/S21 | 52 | L10 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR2: CCI2A/CCI2B input, compare: Out2 output LCD segment output S21 |
| P4.3/TB0.3/S20 | 53 | M12 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR3: CCI3A/CCI3B input, compare: Out3 output LCD segment output S20 |
| P4.4/TB0.4/S19 | 54 | L12 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR4: CCI4A/CCI4B input, compare: Out4 output LCD segment output S19 |
| P4.5/TB0.5/S18 | 55 | L11 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR5: CCI5A/CCI5B input, compare: Out5 output LCD segment output S18 |
| P4.6/TB0.6/S17 | 56 | K11 | I/O | General-purpose digital I/O with port interrupt
Timer TB0 capture CCR6: CCI6A/CCI6B input, compare: Out6 output LCD segment output S17 |
| P4.7/TB0OUTH/SVMOUT/S16 | 57 | K12 | I/O | General-purpose digital I/O with port interrupt
Timer TB0: Switch all PWM outputs high impedance SVM output LCD segment output S16 |
| P8.0/TB0CLK/S15 | 58 | J11 | I/O | General-purpose digital I/O
Timer TB0 clock input LCD segment output S15 |
| P8.1/UCB1STE/UCA1CLK/S14 | 59 | J12 | I/O | General-purpose digital I/O
USCI_B1 SPI slave transmit enable; USCI_A1 clock input/output LCD segment output S14 |
| P8.2/UCA1TXD/UCA1SIMO/S13 | 60 | H11 | I/O | General-purpose digital I/O
USCI_A1 UART transmit data; USCI_A1 SPI slave in/master out LCD segment output S13 |
| P8.3/UCA1RXD/UCA1SOMI/S12 | 61 | H12 | I/O |
General-purpose digital I/O USCI_A1 UART receive data; USCI_A1 SPI slave out/master in LCD segment output S12 |
| P8.4/UCB1CLK/UCA1STE/S11 | 62 | G11 | I/O | General-purpose digital I/O
USCI_B1 clock input/output; USCI_A1 SPI slave transmit enable LCD segment output S11 |
| DVSS2 | 63 | G12 | Digital ground supply | |
| DVCC2 | 64 | F12 | Digital power supply | |
| P8.5/UCB1SIMO/UCB1SDA/S10 | 65 | F11 | I/O | General-purpose digital I/O
USCI_B1 SPI slave in/master out; USCI_B1 I2C data LCD segment output S10 |
| P8.6/UCB1SOMI/UCB1SCL/S9 | 66 | G9 | I/O | General-purpose digital I/O
USCI_B1 SPI slave out/master in; USCI_B1 I2C clock LCD segment output S9 |
| P8.7/S8 | 67 | E12 | I/O | General-purpose digital I/O
LCD segment output S8 |
| P9.0/S7 | 68 | E11 | I/O | General-purpose digital I/O
LCD segment output S7 |
| P9.1/S6 | 69 | F9 | I/O | General-purpose digital I/O
LCD segment output S6 |
| P9.2/S5 | 70 | D12 | I/O | General-purpose digital I/O
LCD segment output S5 |
| P9.3/S4 | 71 | D11 | I/O |
General-purpose digital I/O LCD segment output S4 |
| P9.4/S3 | 72 | E9 | I/O | General-purpose digital I/O
LCD segment output S3 |
| P9.5/S2 | 73 | C12 | I/O | General-purpose digital I/O
LCD segment output S2 |
| P9.6/S1 | 74 | C11 | I/O | General-purpose digital I/O
LCD segment output S1 |
| P9.7/S0 | 75 | D9 | I/O | General-purpose digital I/O
LCD segment output S0 |
| VSSU | 76 | B11, B12 | USB PHY ground supply | |
| PU.0/DP | 77 | A12 | I/O | General-purpose digital I/O, controlled by USB control register. Port U is supplied by the LDOO rail.
USB data terminal DP |
| PUR | 78 | B10 | I/O | USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL. TI recommends a 1-MΩ resistor to ground. See Section 9.7.1 for more information. |
| PU.1/DM | 79 | A11 | I/O | General-purpose digital I/O, controlled by USB control register. Port U is supplied by the LDOO rail.
USB data terminal DM |
| VBUS | 80 | A10 | USB LDO input (connect to USB power source) | |
| VUSB | 81 | A9 | USB LDO output | |
| V18 | 82 | B9 | USB regulated power (internal use only, no external current loading) | |
| AVSS3 | 83 | A8 | Analog ground supply | |
| P7.2/XT2IN | 84 | B8 | I/O | General-purpose digital I/O
Input terminal for crystal oscillator XT2 |
| P7.3/XT2OUT | 85 | B7 | I/O | General-purpose digital I/O
Output terminal of crystal oscillator XT2 |
| VBAK | 86 | A7 | Capacitor for backup subsystem. Do not load this pin externally. For capacitor values, see CBAK in Section 8.3. | |
| VBAT | 87 | D8 | Backup or secondary supply voltage. If backup voltage is not supplied, connect to DVCC externally. | |
| P5.7/RTCCLK | 88 | D7 | I/O | General-purpose digital I/O
RTCCLK output |
| DVCC3 | 89 | A6 | Digital power supply | |
| DVSS3 | 90 | A5 | Digital ground supply | |
| TEST/SBWTCK | 91 | B6 | I | Test mode pin; selects digital I/O on JTAG pins
Spy-Bi-Wire input clock |
| PJ.0/TDO | 92 | B5 | I/O | General-purpose digital I/O
Test data output port |
| PJ.1/TDI/TCLK | 93 | A4 | I/O | General-purpose digital I/O
Test data input or test clock input |
| PJ.2/TMS | 94 | E7 | I/O | General-purpose digital I/O
Test mode select |
| PJ.3/TCK | 95 | D6 | I/O | General-purpose digital I/O
Test clock |
| RST/NMI/SBWTDIO | 96 | A3 | I/O | Reset input (active low)(3)
Nonmaskable interrupt input Spy-Bi-Wire data input/output |
| P6.0/CB0/A0 | 97 | B4 | I/O | General-purpose digital I/O
Comparator_B input CB0 Analog input A0 – ADC (not available on F6632, F6631, and F6630 devices) |
| P6.1/CB1/A1 | 98 | B3 | I/O | General-purpose digital I/O
Comparator_B input CB1 Analog input A1 – ADC (not available on F6632, F6631, and F6630 devices) |
| P6.2/CB2/A2 | 99 | A2 | I/O | General-purpose digital I/O
Comparator_B input CB2 Analog input A2 – ADC (not available on F6632, F6631, and F6630 devices) |
| P6.3/CB3/A3 | 100 | D5 | I/O | General-purpose digital I/O
Comparator_B input CB3 Analog input A3 – ADC (not available on F6632, F6631, and F6630 devices) |
| Reserved | N/A | E5, E6, E8, F4, F5, F8, G5, G8, H5, H8, H9 | Reserved. TI recommends connecting to ground (DVSS, AVSS). | |